CS: L1 Architecture of CPU

Computer Science Architecture of CPU

Program Counter

Holds address of the next instruction to be executed

Incremented (increased by 1) as soon as current instruction is fetched

Memory Address Register

Holds the Address of where the instruction is and the data it uses so it can be fetched from memory later

Knows where to find data in RAM

Memory Data Register

Holds the actual instruction as well as the data it fetched from memory

Holds data found from RAM (from MAR)

Accumulator

Where arithmetic and logic results are temporarily stored

The Arithmetic Logic Unit

Part of CPU

Carries out arithmetic and logic operations

Control Unit

Part of CPU

Controlls everything in CPU- decodes/executes instructions, recieves signals from system clock and directs timing.

Registers

Part of CPU

Main 4: Program counter, Memory Address register, Memory data register and Accumulator

Very fast memory location

Vonn Neumann Architecture

Called the Stored Program Computer

Progam instructions and data used is stored in the same memory

Fetch, Decode, Execute Cycle

Cycle that the CPU operates on

Fetch - Address of next instruction copied from PC to MAR. The instuction that’s there is fetched from memory and copied to MDR. PC is also incremented.

Decode - CU decodes (via Opcode and Operand) + checks if data needs to be fetched. If so, MAR finds address of data which is fetched and copied to MDR

Execute - Executed and result held in Accumulator or Memory

Current Instruction Register (CIR)

Within CU

Holds instruction thats currently being executed/ decoded

Opcode and Operand

Both are within the instruction.

Opcode tells processor what should be done

Operand contains the data address/ data that should be used (copied to either MAR or MDR)