Processor and Control Unit and Pipelining

Comprehensive vocabulary flashcards covering processor types, control units, CPU organization, instruction formats, and pipelining concepts from the lecture notes.

Hardwired Control Unit

A control unit designed using hardware components such as sequential logic circuits or finite state machines (logic gates, flip-flops, decoders) to generate control signals.

Micro-programmed Control Unit

A logic circuit that generates control signals to execute microinstructions using a micro-program stored in control memory.

RISC (Reduced Instruction Set Computer)

A microprocessor architecture associated with hardwired control units that uses a small, uniform set of simple, fixed-size instructions designed to execute in a single clock cycle.

CISC (Complex Instruction Set Computer)

A microprocessor architecture associated with microprogrammed control units that uses a large set of complex, variable-length instructions capable of multiple operations per instruction.

Horizontal Microprogramming

A type of microprogramming where the control memory grows horizontally due to an increase in control signals.

Vertical Microprogramming

A type of microprogramming where the control memory grows vertically due to an increase in control signals and the bits are decoded.

Nano Programming

A technique using two-level control memory providing both the advantages of horizontal and vertical microprogramming.

Single Accumulator Organisation

A CPU organization that uses one special register called an accumulator to store and process data for operations.

General Register Organisation

A CPU organization that uses a collection of high-speed storage elements called a register file to hold operands and intermediate results.

Stack Organisation

A CPU organization that functions on a Last In First Out (LIFO) basis, processing data using the top elements without directly specifying operands.

Stack Pointer (SP)

A register that points to the address of the element located at the top of the stack.

PUSH Operation

An operation used to insert a new data item into the top of the stack, described by the sequence $SP \leftarrow SP-1$ followed by $M[SP] \leftarrow DR$.

POP Operation

An operation used to delete a data item from the top of the stack, described by the sequence $DR \leftarrow M[SP]$ followed by $SP \leftarrow SP+1$.

Program Counter (PC)

A register that points to the address of the next instruction to be executed in the program.

Opcode

A field in an instruction format that specifies the operation to be performed by the CPU, such as addition or data transfer.

Addressing Mode

A field in an instruction format that specifies how to interpret or locate the operand, such as direct or immediate addressing.

Zero Address Instructions

Instructions that do not specify any operands or addresses and typically operate on a stack-based computer using Reverse Polish Notation.

Arithmetic Instructions

Data manipulation instructions that perform four basic operations: addition, subtraction, multiplication, and division, as well as increment and decrement.

Logical and Bit Manipulation Instructions

Instructions that perform binary operations on strings of bits, such as AND, OR, XOR, and Clear (CLR).

Shift Instructions

Operations in which the bits of a word are moved to the left or right, including logical, arithmetic, or rotate-type movements.

Conditional Branch Instruction

A program control instruction that examines values in the condition code register to determine if a specific condition exists before branching.

Subroutine

A program fragment that performs a well-defined task, invoked by another program using CALL and returning control via RET.

NOP (No Operation)

A halting instruction that causes no change in the processor state other than advancing the program counter, often used for timing synchronization.

TRAP

A non-maskable edge and level triggered interrupt with the highest priority and vectored nature.

Pipelining

A mechanism to improve system performance by dividing a problem into subproblems (pipes) and executing tasks in an overlapping manner.

Instruction Fetch (IF)

The first typical pipeline stage where the next instruction is retrieved from memory.

Data Hazard

A pipeline disruption that occurs when an instruction depends on the result of a previous instruction that has not yet been computed.

RAW (Read After Write)

A data dependency also known as True dependency or Flow dependency, occurring when a value produced by one instruction is required by a subsequent instruction.

Structural Hazard

A pipeline hazard occurring when hardware resources are insufficient for concurrent stages.

Forwarding

A technique to handle data hazards by adding special circuitry to the pipeline to pass required values through wires faster than computing them in a segment.