CA2

In MIPS, condition codes are set automatically when a general purpose register is written:

F

The performance of a Multi-cycle MIPS is always better than a Single-cycle MIPS:

F

In Multi-cycle MIPS, intermediate states are recorded in PC and memory:

F

The behavior of the entire processor is specified fully by a finite state machine:

T

In Multi-cycle MIPS, control signals for the next state are determined in current state:

T

In Single-cycle MIPS, the most complex operation slows down everything:

T

By adopting pipelining, more concurrency can be achieved:

T

In Multi-cycle MIPS, most of the datapath is idle when a memory access is happening:

T

The resource contention can be avoided by adopting pipelining:

F

In Single-cycle MIPS, the memory contains both instructions and data:

F