Verilog HDL: Key Concepts, Modeling Styles, and Testbenches

A set of Question-and-Answer flashcards covering Verilog HDL basics, design abstractions, modules, ports, signal declarations, common operators, modeling styles, and testbenches from the lecture notes.

What is Verilog HDL?

A hardware description language used to model electronic systems; describes how a digital system should behave and how it is constructed, supporting parallelism, timing, and concurrency.

List the key uses of Verilog.

Digital circuit design (combinational and sequential); simulation of system behavior; hardware synthesis for FPGA/ASIC.

When was Verilog developed and when did IEEE standardize it?

Developed in 1984 by Gateway Design Automation; IEEE Standard 1364 in 1995.

What is the Verilog design flow?

Specification → HDL Modeling → Functional Simulation → Synthesis → Implementation → Testing.

Name the four Verilog abstraction levels.

Behavioral, Dataflow, Structural, and Switch-Level Modeling.

Explain Behavioral modeling in Verilog.

Describes what the circuit does using control flow (if, case); high-level; not always synthesizable.

Explain Dataflow modeling in Verilog.

Focuses on data movement using continuous assignments; ideal for combinational logic; synthesizable.

Explain Structural modeling in Verilog.

Describes the system as interconnection of components/modules; gate-level; synthesizable.

Explain Switch-Level modeling in Verilog.

Describes circuits using switches (nmos, pmos); lowest level; not commonly used in modern RTL.

What is a Verilog module?

The basic building block; defines a hardware block such as a gate, flip-flop, ALU, or processor.

What is a Verilog port?

Interface through which data enters or exits a module; port types: input, output, inout.

What are the basic Verilog signal data types for signals?

wire for combinational logic; reg for storage inside always blocks.

What is a vector in Verilog?

Multi-bit signals declared as [MSB:LSB], e.g., [3:0].

Example: 4-bit adder output width and declaration.

Output SUM is [4:0] to account for carry; module adder4 ( input [3:0] A, input [3:0] B, output [4:0] SUM ); assign SUM = A + B; endmodule

What is a Verilog testbench?

A module used to simulate and verify a design by applying inputs and observing outputs; used for testing; not synthesized.

What does DUT stand for in testbenches?

DUT = Design Under Test; the unit being tested.

In a testbench, which data type drives inputs?

reg (to be assigned in procedural blocks).

In a testbench, which data type is used for outputs from the DUT?

wire (driven by the DUT or by continuous assignments).

What is the purpose of $display in a testbench?

Prints values/messages once at execution.

What is the purpose of $monitor in a testbench?

Watches for changes and prints values automatically whenever any specified signal changes.

What does #delay do in a testbench?

Pauses execution for a specified simulation time unit before continuing.

What does $finish do in a testbench?

Ends the simulation.

What are $dumpfile and $dumpvars used for?

Create waveform dump files for GTKWave and dump variables for waveform viewing.

What does the concatenation operator do in Verilog?

Uses {} to join signals into a wider vector, e.g., out = {a, b}.

What does the replication operator do in Verilog?

Uses {n{signal}} to repeat a signal n times.

What is the Verilog ternary operator?

Inline conditional: assign out = sel ? a : b.

Explain operator precedence in Verilog (high to low).

Highest: !, ~; then *, /, %; then +, -; then <

Name the arithmetic operators in Verilog with a sample.

+, -, *, /, %; example: assign sum = a + b;

Name the relational operators in Verilog.

==, !=, >,

Name the logical operators in Verilog.

&&, ||, !

Name the bitwise operators in Verilog.

&, |, ~, ^, ~^, ^~

What are the reduction operators in Verilog?

Apply a bitwise operation across all bits of a vector: &, |, ^; e.g., ~&A, ~|A, ~^A.

What are the shift operators in Verilog?

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