MIPS Pipelining

IF

Fetch instruction from memory

ID

Read registers and decode instruction

EX

Execute operation or calculate an address

MEM

Access an operand in memory

add $t0, $t1, $t2

• This instruction performs an addition and writes the result into register $t0.

• Pipelined Execution:

  • In a pipelined architecture, multiple instructions can be processed simultaneously at different stages:

    • Stage 1 (IF - Instruction Fetch): The add instruction is fetched.

    • Stage 2 (ID - Instruction Decode): The add instruction decodes and reads the values from $t1 and $t2.

    • Stage 3 (EX - Execute): The add instruction executes the addition.

    • Stage 4 (MEM - Memory Access): Not applicable for add as it does not involve memory.

    • Stage 5 (WB - Write Back): The result of the add operation is written to $t0.

lw $t0, 0($t1)

load a word from memory into register “$t0". It retrieves a word (4 bytes) from the memory address specified by the contents of register $t1 and stores it in register $t0.