CPU COMPONENTS

CPU

The component in a computer that enables the computer to carry out instructions.

ALU (Arithmetic Logic Unit)

A component of the CPU that performs arithmetic and logic calculations.

CU (Control Unit)

The component in the CPU that directs and coordinates the activities of the entire processor and other components.

Register

The section of high-speed memory within the CPU that stores data to be processed. Faster than cache.

PC (Program Counter)

Stores the RAM address of the next instruction to be fetched.

MDR (Memory Data Register)

Stores the data/instruction that is fetched/read from memory.

CIR (Current Instruction Register)

Holds the instruction currently being decoded and executed. It receives the instruction from the MDR during the fetch stage and passes it to the CU for decoding.

ACC (Accumulator)

Stores the result of mathematical or logical calculations.

MAR (Memory Address Register)

Stores the address/location where data will be read/written/accessed/fetched.

Cache

Stores frequently used instructions and data, so the CPU doesn't always have to fetch them from slower main memory (RAM).

Clock

A tiny electronic pulse generator that synchronises al CPU operations. The clock speed affects how many instructions per second the CPU can process.

Opcode (Operation Code)

Part of a CPU instruction that specifies the action the processor should perform, such as adding or removing data.

Operand

The data or the memory address that the instruction operates on.

Buses

Routes taken to transfer data around the components of the CPU.

Address Bus

A unidirectional bus that carries the memory address that identifies where the data is being fetched from, going from the MAR to RAM.

Data Bus

A bidirectional bus that carries the binary data that actually makes up the instruction between the MDR and RAM.

Control Bus

A bidirectional bus that carries command and control symbols between components of the CPU, such as from the CU to the RAM.

Fetch-Decode-Execute

The cycle carried out in the CPU to complete instructions; an instruction is selected from RAM(fetch), the CPU works out what the instruction means (decode), the CPU carries out the instruction(execute), then a new instruction is fetched from RAM and the cycle repeats.

Fetch Stage (Model Answer)

1. The contents of the PC are copied to the MAR.

2. The read signal is sent by the control unit to the control bus and the contents of the MAR are sent across the address bus.

3. The contents of the memory location stored in the MAR are then sent across the data bus and stored in the MDR.

4. The contents of the MDR are copied to the CIR.

5. The PC is incremented by one.

Decode Stage (Model Answer)

1. The contents of the CIR are sent to the control unit.

2. The control unit then decodes the instruction.

Execute Stage (Model Answer)

1. The registers can be changed in different ways during the execution phase, depending on the instruction.

2. For instance, if the instruction is for a memory location to be read from or written to (LDA or STA), then the address stored within the instruction will be loaded into the MAR. In the case of STA, the data stored in the ACC is sent to the memory.