Loops/Flow Control

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17 Terms

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Pipelining

Widely used way to exploit inherent parallelism inside the CU to speed up the FDE cycle

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Program Counter Register

Contains the address of the next instruction to be executed 

  • PC = PC + 4 during fetch to point to next instruction

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Branching Instruction

Change the PC to point to a different instruction than the next sequential instruction in memory

  • Updated by a different address in the execute phase

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Types of Branches

Unconditional branching: always executes the target instruction

Conditional branch: Perform a jump when a condition is true

<p><span style="font-family: &quot;Open Sans&quot;, sans-serif">Unconditional branching: always executes the target instruction</span></p><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">Conditional branch: Perform a jump when a condition is true</span></p>
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Label

  • Symbols that represent addresses (like pointers, only with a meaning during assembly phase - if not assembly phase then they are a concept)

    • The address given is calculated during assembly

    • Can point both to instructions or data

    • Developers avoid manually calculating addresses

  • A reference to one within the same section uses the program counter plus or minus an offset

  • This is called program-relative addressing

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Example - Unconditional Branch

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If Statement Code

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While Loop Code

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Current Program Status Register (CPSR)

  • An ARM register that records the state of the program

    • Arithmetic instructions will affect its value every time

  • N bit - "negative flag”: instruction result was negative

  • Z bit -"zero flag”: instruction result was zero

  • C bit - "carry flag”: Instruction causes a carry-out or borrow

  • V bit - "overflow flag”: Instruction produces an overflow in 2's complement numbers

<ul><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">An ARM register that records the state of the program</span></p><ul><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">Arithmetic instructions will affect its value every time</span></p></li></ul></li><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">N bit - "negative flag”: instruction result was negative</span></p></li><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">Z bit -"zero flag”: instruction result was zero</span></p></li><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">C bit - "carry flag”: Instruction causes a carry-out or borrow</span></p></li><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">V bit - "overflow flag”: Instruction produces an overflow in 2's complement numbers</span></p></li></ul><p></p>
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CoMPare

Perform a comparison (substraction), updates the CPSR and discards the result

<p><span style="font-family: &quot;Open Sans&quot;, sans-serif">Perform a comparison (substraction), updates the CPSR and <strong>discards </strong>the result</span></p>
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CPSR and Arithmetic Instructions

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Conditional Branching

  • Branch instructions use a single 24-bit signed immediate operand

  • The remaining 24-bit two’s complement imm24 field is used to specify an instruction address relative to PC + 8

  • Branching instruction variation: BEQ, BNE,…

  • Their execution depends on the CPSR condition bits

    • If condition is false, then branch is skipped

  • You can construct any branch condition with the mnemonics in the table

<ul><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">Branch instructions use a single 24-bit signed immediate operand</span></p></li><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">The remaining 24-bit two’s complement imm24 field is used to specify an instruction address relative to PC + 8</span></p></li></ul><ul><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">Branching instruction variation: BEQ, BNE,…</span></p></li><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">Their execution depends on the CPSR condition bits</span></p><ul><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">If condition is false, then branch is skipped</span></p></li></ul></li><li><p><span style="font-family: &quot;Open Sans&quot;, sans-serif">You can construct any branch condition with the mnemonics in the table</span></p></li></ul><p></p>
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Branch Mnemonics

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Branch Example - if-then-else

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Branch Example - when

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Conditional Instruction

  • ADDEQ, ADDNE

Thumb-2 introduced the If-Then (IT) instruction

  • providing conditional execution for up to four consecutive instructions. The conditions might all be identical, or some might be the inverse of the others

  • Instructions within an IT block must also specify the condition code to be applied

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Conditional Execution Example

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