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Hard disk (magnetic)
Read and written to using two magnetic states (polarised and unpolarised). Not very portable due to size, they have a huge capacity, medium speeds compared to flash and optical, cheap, not durable due to moving parts.
Optical
Read and written to from lasers, examples are CD's, DVD's, Blu-Ray. They are portable due to size, not durable as they can be scratched easily, little storage, cheap, slow
SSD (Flash)
Stored in blocks which form pages of 1's and 0's. Very portable due to its size, durable due to no moving parts, fast, expensive, medium-high capacity compared to flash and optical.
Volatile
Loses content with power loss
Non-volatile
Keeps content with power loss
RAM (volatile)
Fast and stores the programs and data that the computer is currently using.
ROM (non-volatile)
Stores information that is permanently required to boot up and run the computer.
Opcode
Determines type of instruction and hardware needed.
Operand
Holds either the address of the data to be used or the actual data to be operated on.
Register
Temporarily store data and control information
Arithmetic logic unit (ALU)
Performs all the logical operations and calculations.
Control unit (CU)
Coordinates all activities within the CPU and sends control signals.
Program counter (PC)
Holds the next instruction to be executed. It increments by one during each cycle.
Accumulator
Data or control information is stored in it. Results from ALU can be temporarily stored here.
Memory address register (MAR)
Holds the address of the memory location of data or instruction which is going to be fetched or written and sends addresses through address bus.
Memory data register (MDR)
Temporarily stores the data that is read from or written to memory. Data to and from memory always travels through data bus.
Current instruction register (CIR)
Holds the current instruction being executed. Contents of MDR is copied to the CIR if it is an instruction. Divides the opcode and operand. Opcode - instruction to be executed, operand - data or memory location to execute instruction.
Control bus
Carrys command and control signals to and from each component of the CPU.
Data bus
Carrys 1's and 0's that make up the information being transmitted.
Clock speed
Number of cycles per second, measured in Hz for example 3.2 Ghz clock speed = 3.2B instructions can be fetched per second.
Cores
How many instructions can be processed simultaneously for example a quad core processor would be able to process 4 instructions simultaneously.
Cache
Temporary storage of data and instructions being read and written from. This is much faster than main memory due to it being much closer to the CPU compared to RAM. As Cache fills up unused data or instructions are constantly being replaced with newer ones.
Pipelining
Where the processor does multiple things at once to improve processor speed, this is done by executing an instruction while decoding a different instruction and fetching a different instruction and it starts a new cycle each step of the fetch-decode-execute cycle.
Contemporary processor architecture
Combines Neumann and Harvard together.
Von Neumann
Data and programs share the same memory. One bus is used to transfer data and instructions. Programs can be optimised in size, Used in conventional processors in PC's and servers.
Harvard
Instructions and data are held in separate memories to allow the next instruction to be read while data is currently being read or written from. Parallel data and instruction buses may be used. Programs tend to be too large. Used in speech and image processing systems.
CISC
Complex, multiple instructions per line. It is quicker, there is little work for the compiler, code is short.
RISC
Reduced, one instruction per line. Easy to debug, hardware is simple to build, pipelining is possible, high processor performance.
Graphical processing unit (GPU)
Performance extremely simple mathematical calculations but is unable to do tasks the CPU can. Its uses can be image processing, machine learning, and more simple repetitive tasks.
Multicore and Parallel systems
Multicore CPU's have multiple cores that can complete instructions separately which increases performance. Parallel systems split a job into several subtasks which are simultaneously carried out by each core in the system.
Virtual memory
Storing information remotely where it can be accessed by any computer for example the cloud. It is convenient to access and share but it is limited by user network speeds, high costs, risks of information being stolen or tampered with.
Virtual storage
Using the hard disk as though it were an extension of memory to free up more RAM for current programs.
Address bus
Carrys memory addresses that identify where the data is being read/written.
Fetch-Decode-Execute Cycle
Fetch -
1. The address of the next instruction is copied from the PC to the MAR and PC is incremented by one.
2. Address is sent along the address bus to main memory while it waits for a signal from the control bus.
3. CU sends a read signal along the control bus to main memory; data is assigned by the address.
4. Data is sent to MDR along the data bus.
5. Contents of MDR is copied to the CIR.
Decode -
1. The instruction is held in the CIR to be decoded.
2. Instruction is split into opcode and operand.
3. Operand may hold the address of the data to be used within the operation which will then be copied to the MAR, or the actual data to be operated on which will be copied to the MDR, the data to be operated on may be passed onto the ALU to execute or passed onto the accumulator to temporarily store it.
Execute -
1. Instruction/opcode is carried out on the operand