CPU Structure & Instruction Flashcards

What role Arithmetic Logic Unit (ALU) in CPU ?

The ALU performs all arithmetic and logical operations, such as addition, subtraction, and comparisons.

What is the Control Unit (CU) in a CPU?

The CU directs and controls the operations of the CPU by managing data flow and coordinating different components.

What is the function of the Memory Unit (MU) in a CPU?

The MU stores and retrieves the data required for execution, such as instructions and operands.

What is a single-core processor?

A processor with one core that can handle one operation at a time, less efficient for multitasking.

What is the difference between dual-core and quad-core processors?

Dual-core processors have two cores, while quad-core processors have four, offering better multitasking and performance.

What are the stages of the instruction cycle in CPU operation?

The stages are Fetch, Decode, Execute, Memory Access, and Registry Write-Back.

What is pipelining in CPU architecture?

Pipelining allows the CPU to execute multiple instructions in parallel by overlapping stages of instruction processing.

What is the purpose of branch prediction in pipelined CPUs?

It predicts the direction of branches in instructions to avoid pipeline stalls, improving execution efficiency.

What is an example of a pipeline hazard?

Data hazards occur when an instruction depends on the result of a previous one still being processed.

What does instruction cache miss refer to?

A situation where the CPU fails to find the required instruction in its cache, slowing down execution.

What is Instruction-Level Parallelism (ILP)?

ILP allows multiple instructions to be processed simultaneously, but it has limitations beyond which adding hardware doesn’t significantly speed up execution.

What is RISC (Reduced Instruction Set Computer)?

RISC is a CPU design that uses a small, simple set of instructions, typically operating on data in registers.

How does pipelining improve CPU efficiency?

It overlaps the stages of different instructions, allowing the CPU to process instructions faster by using resources efficiently.

What is a dual-stage instruction pipeline in RISC?

It divides instruction execution into fetch and execute stages to allow parallel processing of instructions.

What are pipeline stages?

These are different processing steps in the pipeline, such as Fetch, Decode, Execute, etc., that run in parallel for different instructions.

What is a six-stage CPU instruction pipeline?

It divides instruction execution into six stages, including fetch, decode, and execute, to optimize processing.

What are structural hazards in pipelined CPUs?

These occur when two instructions require the same hardware resource at the same time, causing delays.

How does pipelining affect task execution time?

While individual tasks may not speed up, pipelining reduces the average task execution time by processing multiple instructions in parallel.

What is a control hazard in CPU pipelining?

It occurs when the pipeline must wait for the outcome of a branch instruction to know which path to take next.

What is the difference between RISC and CISC (Complex Instruction Set Computer)?

RISC uses a small, simple set of instructions, while CISC uses a more complex set that can perform multiple operations in a single instruction.