ECS 154b Assesment 2 Review

MIPS uses load/store instructions, with 3 instruction formats - R, I and J. If you want to do a branch instruction, which format would you use

I

When we talk about the number of operands in an instruction (a 1-operand or a 2-operand instruction, for example), what do we mean

how many operands are explicitly specified in that instruction

Our multicycle 8-bit design uses a single memory, but the single cycle version design has two. Why is that?

you cannot go into memory twice in a single cycle

Registers are faster than main memory. What is another advantage to using registers? What is one disadvantage?

advantage: deterministic/short id

disadvantage: fixed size/ separate address space

In the MIPS processor, there are branches and there are jumps.

a. For a jump, explain exactly how the new address to be placed in the PC is created/calculated.

replace the lower 28 bits of the PC with the lower 26 bits of the instruction, shifted by 2 bits

In the MIPS processor, there are branches and there are jumps.

For a branch that is taken, explain exactly how the new address to be placed in the PC is created/calculated.

compute operands for equality

compute the branch target address (pc plus the 16 bit sign extended offset field in the instruction)

We want to use microcode to provide the control signals for a machine which has 21 control signals and a 7-bit opcode. Assuming there are 12 states in the State Transition Diagram and you are using the simplest microcode configuration,

a. How many entries would the microcode memory have?

b. How wide would each entry be? (Drawing a picture might be useful).

a) 12 states requires 4 bits, and a 7 bit opcode => 2^7×2^4=2^11

b) 21 control signals + 4 bits for states = 25 wide

Is it true that more powerful instructions (instructions that do more) mean higher performance? Explain your answer.

no, performance is inst/prog x time/cycles x cycles/instruction. while the inst/prog would be lower, the cycles/instruction and time/cycles may be higher in a way that lowers performance

What are the 3 pipeline hazards? Which one can be eliminated by providing more resources?

structural, data and control. structural

What are the 3 types of data hazards? Which one can be dealt with by using forwarding?

RAW, WAR, WAW; RAW

How do you "squash" (or undo) an instruction in a pipelined machine? (What must be prevented from happening?)

prevent it from writing to memory

Why do we care about techniques like forwarding, since hazards can be avoided by introducing stalls in the pipeline? Why do we want to avoid stalls?

Stalls make the entire program take longer

We want to use microcode to provide the control signals for a given machine which has 23 control signals and a 6-bit opcode. Assuming there are 8 states in the State Transition Diagram and you are using the simplest microcode configuration,

a. How many entries would the microcode memory have?

b. How wide would each entry be? (Drawing a picture might be useful).

a) 8 states require 3 bits, and a 6 bit opcode. 2³+2^6=2^9

b) 23 control signals + 3 bits for states = 26

In your first design of a 5-stage pipeline (F,D,E,M,W), F takes 29 time units, D takes 32, E takes 60, M takes 31, and W takes 28.
a) What will the clock cycle time be for this pipeline?

b) Is it a balanced pipeline? If not, explain what you could do to fix it. What would the cycle time be now?

a) 60

b) No, I would split E into E1 and E2 making them 30 each, 32

In your first design of a 5-stage pipeline (F,D,E,M,W), F takes 24 time units, D takes 26, E1 takes 13, E2 takes 14, M takes 24, and W takes 25.
a) What will the clock cycle time be for this pipeline?

b) Is it a balanced pipeline? If not, explain what you could do to fix it. What would the cycle time be now?

a) 26

b) no, I would combine E1 and E2; 27