CPE109-4: ADVANCED TOPICS IN INPUT/OUTPUT

A special pin toggled by the CPU to switch from using the address bus for accessing RAM, to using the address bus to talk to other semi-intelligent chips.

special I/O pin

A series of pins on the processor that are used to get data into, or out of, the processor chip itself.

Data Bus

A component that gathers all the hardware interrupt events from the SOC and platform and then presents the events to the processor.

Interrupt Controller

The line used by external devices when they need the attention of the processor.

Interrupt Request Line (or IRQ Line)

Interrupts that can be selectively enabled or disabled by the software.

Maskable interrupts

Interrupts that the software can never disable. It is most often used to perform the DRAM refresh on memory chips.

Non-maskable interrupt

A technique where instead of asserting the I/O pin and addressing a data port, the processor just accesses a memory address directly.

Memory mapped I/O

Transfers executed by the processor on the external device without any assistance from the main processor.

Direct Memory Access (DMA)

The first interrupt mechanism in the Intel architecture platform.

8259 Programmable Interrupt Controller

The second, more modern interrupt controller in the Intel architecture platform.

Advanced Programmable Interrupt Controller (APIC)

A specification language, not a programming language, used after you draw your schematic and state machines.

Verilog

The keyword used in Verilog to denote a hardware net.

wire

The state of Arduino (ATmega) pins when configured as INPUT with pinMode().

high-impedance state

The state of Arduino (ATmega) pins when configured as OUTPUT with pinMode().

low-impedance state

The argument used in pinMode() to access the internal pull-up resistors of the ATmega microcontroller.

INPUT_PULLUP

The maximum amount of current ATmega pins can source (provide current) or sink (absorb current) to other devices/circuits.

40 mA (milliamps)

Once the CPU has placed the proper address on the address bus and it asserts the special I/O pin, all ________ are temporarily disabled, and the external I/O chips are read or written from instead.

RAM chips

In Memory Mapped I/O, the external device can have a small amount of ________ or ________ that the processor just reads or writes as needed.

RAM or ROM

Keep in mind that many DMA enabled systems have a limit on the maximum size transfer allowed (often ________).

64K

Once the DMA transfer is complete, the external device usually notifies the main processor of this by raising an ________.

interrupt request

In Verilog, a value of 0 means ________.

Logic zero

In Verilog, a value of 1 means ________.

Logic one

In Verilog, a value of X means ________.

Unknown logic value

In Verilog, a value of Z means ________.

High impedance, floating

If a pull-down resistor is used on an INPUT pin, the input pin will be LOW when the switch is open and ________ when the switch is closed.

HIGH

If a pull-up resistor is used on an INPUT pin, the input pin will be HIGH when the switch is open and ________ when the switch is closed.

LOW

Enumerate the two types of interrupt lines on all processors.

Maskable interrupts; Non-maskable interrupt

Enumerate the four logic values in Verilog and their corresponding meanings.

0 (Logic zero); 1 (Logic one); X (Unknown logic value); Z (High impedance, floating)

Enumerate the two resistors that can be used for pins configured as INPUT to define their logic levels based on switch states.

pull-down resistor; pull-up resistor

Enumerate the two Intel Architecture Specific interrupt controllers mentioned.

8259 Programmable Interrupt Controller; Advanced Programmable Interrupt Controller (APIC)