1.4- instruction cycles

Instruction Cycle

• The instruction cycle (fetch–decode–execute cycle) is how the CPU processes instructions from boot-up to shutdown.

• Composed of three main stages:

  1. Fetch Stage

  2. Decode Stage

  3. Execute Stage

Role of Components

• Program Counter (PC): Holds the address of the next instruction.

• Memory Address Register (MAR): Stores the address to read/write data.

• Memory Data Register (MDR): Holds data fetched from or to be written to memory (also known as Memory Buffer Register).

• Current Instruction Register (CIR): Temporarily holds the fetched instruction.

• Control Unit (CU): Decodes instructions and sends control signals.

• Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.

• Floating Point Unit (FPU): Handles floating-point operations.

Summary of Stages

1. Fetch Stage:

   • The instruction is fetched from the memory address in the PC, stored in CIR, and PC is incremented for the next instruction.

2. Decode Stage:

   • The CU decodes the instruction; if it requires data, an effective address is calculated and data is fetched if needed.

3. Execute Stage:

   • CU sends control signals to execute actions, such as mathematical operations or reading values.

4. Repeat Cycle: The process continues for the next instruction.

Fetch Cycle Steps

1. Move the address in the PC to the MAR.

2. Place the MAR address on the address bus and issue a READ command. The data is copied to MDR and PC is incremented.

3. Move content of MDR to CIR

Instruction Types

• Processor-Memory: Transfer data between CPU and memory.

• Processor-I/O: Transfer data to/from peripheral devices.

• Data Processing: Perform arithmetic or logic operations.

• Control: Alter the execution sequence based on instructions