CSE381 T or F

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7 Terms

1
New cards

False

For a given capacity and block size, a set-associative cache implementation will typically have a lower hit time than a direct-mapped implementation.

2
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False

In a Write-Through cache, a read miss always causes a write to the lower memory level.

3
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False

High associativity in a cache reduces compulsory misses.

4
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True

RAID systems can have catastrophic failures.

5
New cards

False

SRAMs are optimized for storage density.

6
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True

TLBs are placed on a special cache memory.

7
New cards

False

For a given capacity and block size, a set-associative cache implementation will typically have a lower hit time than a direct-mapped implementation.