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Vocabulary flashcards covering charge trap flash technology, storage cell design, and semiconductor manufacturing processes from the lecture transcript.
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Charge Trap Flash
A three-dimensional memory array technology where hundreds of storage cells are stacked on top of each other to achieve high storage density.
Storage Cell
A memory unit in charge trap flash that is 100nm wide and stores 3 bits of data by trapping electrons within a thin silicon nitride layer.
Silicon Nitride
A thin horizontal layer material in flash memory chips that traps electrons to store data at every vertical column intersection.
Read Right Control Wires
Wires connected to vertical columns that select specific memory layers and step down like stairs along the sides of the memory array.
Silicon Wafer Thinning
A manufacturing step where the bottom of a silicon wafer is ground down until each die is reduced to a thickness of 40μm.
Controller Die
An interconnected chip component that links the stack of NAND flash dies to external contact pins for data transfer.
Epoxy Packaging
The protective encapsulation process where the entire interconnected semiconductor assembly is sealed in epoxy and housed in a thin plastic shell.
Artificial Neuron Transistor
A modified transistor created by a lab accident, as reported in the July issue of IEEE Spectrum, designed to lower AI energy consumption.