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Arithmetic and Logic Unit
Completes all arithmetical and logical operations.
Control Unit
Directs the operations of the CPU.
Registers
Small memory cells that operate at very high speeds
Purpose of the Program Counter
Holds the address of the next instruction to be executed.
Purpose of the Accumulator
Stores the results from calculations in the ALU
Purpose of the Memory Address Register
Holds the address of the location that is to be read from or written to
Purpose of the Memory Data Register
Temporarily stores the data that has been read or that needs to be written
Purpose of the Current Instruction Register
Holds the current instruction being executed, divided up into operand and opcode
Buses definition
Set of parallel wires which connect two or more components inside the CPU
Data bus definition
Bi-directional bus used for transporting data and instructions between components
Address bus definition
Bus used to transmit the memory addresses specifying where data is to be sent or retrieved from
Control bus definition
Bi-directional bus used to transmit control signals between internal and external components.
What do the control signals include?
Bus request
Bus grant
Memory write
Memory read
Interrupt request
Clock
What is assembly language?
Uses mnemonics to represent instructions. This is a simplified way of representing machine code
What is assembly language divided into?
Operand: contains the data or the address of the data
Opcode: specifies the type of instruction to be executed
What is pipelining?
The process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously
What is the purpose of pipelining?
To reduce the amount of CPU which is kept idle
What is the fetch-decode-execute cycle?
The sequence of operations that are completed in order to execute an instruction
What happens during the fetch phase?
Address from the PC is copied to the MAR
Instruction held at that address is copied to the MDR
Simultaneously, the contents of the PC are incremented
The contents of the MDR is copied to the CIR
What happens in the decode phase?
The contents of the CIR are split into operand and opcode
What happens in the execute phase?
The decoded instruction is executed
What are the three factors affecting CPU performance?
Clock speed
Number of cores
Cache memory
How does the clock speed affect CPU performance?
It's the time taken for one clock cycle to complete. The faster the clock speed, the more instructions can be carried out in the same time frame
How does the number of cores affect CPU performance?
A core is an independent processor that runs it's own fetch-execute cycle. More cores means more cycles can be completed and instructions executed at once
How does the cache memory affect CPU performance?
Cache is the CPU's onboard memory that stores frequently used instructions. It's much faster than regular memory so larger cache memory means more instructions can be accessed quicker
What are the two types of computer architecture?
Von Neumann Harvard
What is von Neumann architecture?
Architecture that includes the basic components of the computer and processor in which a shared memory and shared data bus is used for both data and instructions
What is harvard architecture?
Architecture that has physically separate memories for instructions and data
Advantages of von Neumann
Cheaper to develop
Programs can be optimised in size
Advantages of harvard
Quicker execution as data and instructions can be fetched in parallel Memories can be different sizes which makes efficient use of space Avoids the issue of bottlenecking
What is contemporary processing?
Uses a combination of both Harvard and Von Neumann architecture. Von Neumann is used when working with data and instructions in main memory, but uses Harvard to divide the cache into instruction cache and data cache
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