ECEN421 - Unit #5 Quiz

Why Synchronous Serial Communication is Important

faster speed, data transmitted and received simultaneously, straightforward synchronization of transmitter and receiver, more transmission rate options

Serial Peripheral Interface (SPI)

synchronous protocol consisting of “master” and “slave” transceivers. Used when update-speed is important

Master Transceiver

initiates communication and provides the clock signal

Slave Transceiver

responds to the request

Possible SPI networks

single master/single slave (3-wire), single master/multiple slaves (4-wire), multiple master/single slave (4-pin)

SPI I/O Pins (4)

SIMO, SOMI, CLK, STE

SIMO

slave gets input data and master sends output data

SOMI

master gets input data and slave sends output data

CLK

the SPI clock generated by the master device. Ensures synchronization between master and slave devices

STE (Slave Transmit Enable)

used to enable the chosen master in the multiple master mode or chsen slave in the multiple slave mode

SPI Transmit/Receive Operations

Data must always be recieved from the slave while the master is transmitting (or vice versa)

Three Wire Mode for One-to-One Communication

Master SCLK and SIMO to Slave, Slave SOMI to Master

SPI Operations Master

For 7 or 8 bits, Transmit, TXBUF register, TX Shift register, SIMO, RX shift register, RXBUF

SPI Operations Slave

For 7 or 8 bits, TXBUF, TX shift register, SOMI, clock edge, RX shift register, RXBUF,

4-Pin SPI Mode Communication

multi-master (active by STE bits, SIMO and CLK as inputs), multi-slave (active by STE bits, SOMI as input), can disable slave in a single master/single slave setup

Advantages of SPI

fastest protocol compared to UART and I2C, supports full-duplex communication, no individual addresses for slaves because of CS or SS, only master device supported at a time, shared clock signal ensures synchronization

Disadvantages of SPI

more port pins occupied limit to devices, no error check like UART (parity bit), one master at a time, each extra slave requires an additional dedicated pin on master for CS or SS, no confirmation of receipt of data, slowest devices determines transfer speed, no flow control

SPI When Update Speed is Important

Flash EEPROM Programming, Audio and Video codecs, Color LCD Module, Standard high-speed synchronous communications (USB, ethernet, CAN)

ESP32 SPI Controller

4 peripheral devices (SPI0, SPI1, HSPI, VSPI), SPI0 and SPI1 write to internal flash chip, HSPI and VSPI external interfacing use

SPI Communication Pins

(Red/Peach color) HSPI_CLK/MISO/MOSI/CS(14, 12, 13, 16), VSPI_MOSI/MISO/CLK/CS(23, 19, 18, 5)

Why I2C is Important

2-wire bidirectional synchronous protocol, low pin count, easy many-to-many communication, open-drain shared-bus scheme is HW scalable, optimized for low cost & speed

Inter-Integrated Communications (I2C)

can be used between multiple masters and slaves, two pins (serial data and serial clock), pins connect to positive supply voltage

Open-drain Technology for Data Clock Lines

supports multiple drivers on same line using NMOS transistor

Communication by only two I2C I/O pins

master and slave devices represented by address values, transmit and receive operations done on single SDA line, SCL clock generated by master

I2C Transmit/Receive operations

data transfer carried out byte-by-byte during one SCL pulse, starts when master sends start condition to slave, slave address transmitted by master according to addressing mode

I2C 7-bit addressing mode

sent in one byte, when R/W bit is zero then master will transmit, when R/W is one then master will receive, acknowledgement ACK is sent by receiver

I2C 10-bit addressing mode

sent in two bytes, first byte formed by 11110 follwed by R/W and first two bits of slave address, second byte contains remaining eight bits of slave, ACK sent

I2C Transmit/Receive Operations

busy bit set to indicate bus is busy, data transfer complete then master sends communication stops, four different operation options

Master device writes data to slave device

start, slave address, write, ACK, data ACK, data, ACK, end

Master device reads data from slave device

start, slave address, read, ACK, data, ACK, data, NAK, end

I2C Slave transmitter mode

I2COA register, bit seen to be one if match, TXIFG reset and ACK bit sent, data written to TXBUF

I2C Slave receiver mode

I2COA register, STTIFG set and STPIFG reset if match, TR bit reset, ACk bit sent, SDA pin transfers to RX shift register, RXBUF, RXIFG,

More about I2C slave receiver mode

master can send new data byte and transfer proceeds, send a stop condition where STPIFG is set and STTIFG is reset, master can send a restart condition, slave device can send a NACK

I2C Master Mode

device configured as master by MST control bit, target slave address written to I2CSA register with SLA10 bit, if master is transmitter then TR must be set, if receiver then bit must reset

I2C Master Transmitter mode

generates start condition if TXSTT bit set by software, slave address transmitted with R/W bit being zero, ACK bit expected from slave, TXSTT bit reset

More about I2C Master Transmitter mode

slave can send ACK bit, new data byte transmitted, master can generate a stop condition after last ACK bit is received, slave can send a NACK bit

I2C Master Receiver mode

master generates start if TXSTT is set, TR bit is reset, slave address is transmitted with R/W bit being one, ACK bit sent by slave, TXSTT bit reset , master can send ACK bit, master can generate stop by setting TXSTP and sending NACK bit, reset would be TXSTT and NACK

Disadvantages of I2C

limited speed because of pull-up resistors for open-drain design, requires more space, software becomes complex with more devices

Contemporary Applications of I2C: Low-Speed/short distance communication

low-speed sensors, low-speed displays, accessing DACs and ADCs, Memory ICs

I2C Communication pins

(light green) I2C_SCL/SDA (22, 21)