ENG210 Computer Architecture: CPU & Memory

A comprehensive set of 250 flashcards covering key concepts of Computer Architecture, specifically on CPU and memory components, processes, and enhancements.

What are the major components of the CPU?

ALU (Arithmetic Logic Unit), CU (Control Unit), Memory Management Unit, and I/O Interface.

What does the ALU perform?

Calculations, comparisons, and executes logical operations (AND, OR, NOT, XOR).

What is the role of the Control Unit (CU)?

It performs the fetch/execute cycle, accesses program instructions, issues commands to the ALU, and manages data movement.

What does the Memory Management Unit do?

It supervises the fetching of instructions and data from memory.

What are registers in the CPU?

Small, permanent storage locations with specific functions that hold data, addresses, or instructions.

What is the function of General Purpose Registers?

They hold intermediate results or data values and are visible to the user or program.

What is the Program Count Register (PC) also known as?

Instruction Pointer.

What does the Instruction Register (IR) do?

Stores the instruction fetched from memory.

What is the function of the Memory Address Register (MAR)?

Holds the address of a memory location to be accessed.

What does the Memory Data Register (MDR) hold?

Temporarily holds data that is being transferred to or from memory.

Define volatile memory.

Memory that requires constant power to maintain the stored information, like DRAM.

What does RAM stand for?

Random Access Memory.

Describe Dynamic RAM (DRAM).

It is the most common type of RAM, cheaper, less power-consuming, volatile, and needs to be refreshed often.

What is Static RAM (SRAM)?

Faster and more expensive than DRAM and is often used as cache memory.

What is ROM?

Read-Only Memory, which holds software expected to remain unchanged.

What is EEPROM?

Electrically Erasable Programmable Read-Only Memory.

What does cache memory do?

Stores frequently accessed data for quicker retrieval, improving CPU efficiency.

Explain the Fetch-Execute Cycle.

A two-step process where the CPU fetches a program instruction from memory and executes it.

What happens during the Fetch Phase?

The address from the Program Counter (PC) is placed in the MAR, the instruction is loaded into IR, and the PC is incremented.

What memory types are nonvolatile?

ROM, EEPROM, and Flash Memory.

What is a bus in computer architecture?

A physical connection that transfers data from one location to another.

What are the four types of bus signals?

Data, Addressing, Control signals, and Power.

What is pipelining in CPU architecture?

An assembly-line technique that allows overlapping fetch-execute cycles for multiple instructions.

Define scalar processing.

Average instruction execution is approximately equal to the CPU clock speed.

What is superscalar processing?

The ability of a CPU to execute more than one instruction per clock cycle.

Explain the purpose of the Fetch Unit.

Handles instruction fetching and decoding from memory.

Describe the Execution Unit's role.

Executes the instructions received from the decode unit.

What are the advantages of cache memory?

Higher hit ratio leading to improved execution speed due to locality of reference.

Define multiprocessing in computer architecture.

Using two or more CPUs to increase processing power.

What is master-slave multiprocessing?

One master CPU manages the system and assigns tasks to slave CPUs.

Define symmetrical multiprocessing (SMP).

Each CPU has equal access to resources and can run processes independently.

What are the drawbacks of master-slave multiprocessing?

The master CPU can become a bottleneck and failure can lead to complete system failure.

What is the significance of performance advantages from cache memory?

It allows for faster data access, minimizing the time the CPU waits for data retrieval.

What causes latency issues in memory access?

Differences in speed between the CPU processes and memory access speeds.

What types of operations do CPUs perform?

Data movement, arithmetic, logic operations, and I/O machine control.

What is the function of the instruction set?

Defines the functions performed by the processor and differentiates computer architectures.

Give an example of a special-purpose register.

Program Count Register (PC) or Instruction Register (IR).

How does the Control Unit interact with the ALU?

It delivers data to the ALU and informs it which operation to perform.

What is a hit ratio in cache memory?

The ratio of successful data retrievals from cache to total requests.

What is meant by instruction reordering?

The rearrangement of instruction execution to avoid delays due to dependencies.

Explain memory interleaving.

Partitioning memory into subsections for faster access through simultaneous addressing.

How does a CPU know which instruction to execute next?

By using the Program Counter (PC) to point to the next instruction address.

What is meant by 'out-of-order processing'?

Executing instructions not strictly in the order they appear, to optimize pipeline performance.

What does the CPU's clock speed determine?

The rate at which the CPU can execute instructions.

What happens when there is a cache miss?

The cache controller must fetch the required data from the main memory.

Define the term 'bus throughput.'

The data transfer rate in bits per second for a bus.

What is the role of the cache controller?

It manages the flow of data between the cache and main memory.

How does the ALU support comparisons?

By executing logical operations to evaluate conditions like greater than or equal.

What does pipelining help improve in CPU performance?

It reduces the execution time of sequences of instructions by overlapping cycles.

What is the impact of data dependencies in CPU execution?

They can stall the instruction pipeline, affecting processing speed.

How is instruction format significant in computer architecture?

It defines the layout of the instructions, including opcode and operand locations.

What is the difference between a fixed and variable instruction size?

Fixed size means all instructions have the same length; variable size can vary.

What do flags in the CPU indicate?

They track conditions like overflow, carry, and errors during operations.

How many instruction types does a CPU generally support?

Multiple types including data movement, arithmetic, and control instructions.

What is a bus interface unit?

A component that manages data exchanges between the CPU and memory or peripherals.

What is the purpose of a status register?

To hold information about the current state of operations in the CPU.

What does 'locality of reference' mean in caching?

The tendency of a processor to access a small set of memory locations frequently.

What is branch prediction?

A technique to guess the outcome of a branching operation to improve pipeline efficiency.

What is the function of an instruction pointer?

To track the address of the next instruction to be executed.

What are point-to-point buses?

Connections that link a single source to a single destination.

Define a multipoint bus.

A bus that connects multiple devices to a single communication channel.

What is the primary purpose of cache lines?

To serve as a unit of transfer between storage and cache memory.

How does the memory bus affect data transfer?

It impacts the speed and bandwidth for data communication in the system.

What is the role of a cache line in cache memory?

To organize data retrieved from main memory for better efficiency.

What setting allows cache memory to deliver better performance?

A higher hit ratio and frequent data locality within processes.

Why is the CPU unable to access memory directly?

The bus and cache memory act as intermediaries to facilitate access to RAM.

What are common application outcomes of high-speed memory access?

Faster program execution and improved overall system performance.

What can cause CPU bottlenecking in a master-slave system?

The master CPU being overwhelmed with too many requests from slave CPUs.

What constitutes an effective architecture in multiprocessor systems?

Balanced distribution of processes and efficient resource sharing.

What is the functional difference between pipeline execution and superscalar processing?

Pipelining overlaps execution phases, while superscalar executes multiple instructions simultaneously.

Define the term 'observation of bottlenecks' regarding CPU usage.

Identifying moments where processing efficiency drops due to resource limitations.

How does instruction size affect pipeline architecture?

Larger and varied sizes complicate simultaneous instruction processing.

What does a 'fetch signal' do during memory accesses?

It prompts the memory to send a specific piece of data requested by the CPU.

What is the impact of using different clock signals for CPUs?

It can lead to synchronization issues and performance inconsistencies.

What defines cache's hit consistency across multiple processes?

Sharing a unified cache memory to maintain state across multiple cores.

How is addressability of a system determined?

By the number of bits in the MAR and the span of addressable locations.

What does a sample CPU organization look like?

It includes an execution unit, fetch unit, memory bus, and cache.

Explain the working of the Cache Write Back strategy.

Data is written back to the main memory only when necessary, improving write speeds.

What is the functionality of Address Decoders in relation to memory?

They translate logical addresses to physical addresses for data access.

How does computer architecture distinguish between various CPU designs?

Through differences in instruction sets, execution speeds, and parallel processing capabilities.

Why is managing CPU registers crucial for performance?

To optimize the speed of data retrieval and processing within the CPU.

Define the significance of Bus Characteristics in system performance.

They dictate the efficiency of data throughput and control mechanisms.

What is meant by 'Arithmetic Logic Unit' in processor design?

The component responsible for performing mathematical and logical operations.

Explain how online performance monitoring can alleviate bottlenecks.

By adjusting workloads dynamically based on real-time CPU usage.

What are power reduction features in modern CPUs?

Techniques such as dynamic frequency scaling and sleep modes to conserve energy.

Identify the role of Conditional Branching in CPU operation.

To enable decisions in program flow based on specific boolean evaluations.

What are the challenges posed by data dependencies?

They can hinder pipeline execution efficiency and require careful management.

Define cache coherence in multiprocessor systems.

Ensuring that multiple caches have a consistent state regarding shared data.

How does a computer classify immediate and indirect addressing modes?

Immediate uses explicit values, while indirect fetches values from a location.

What is the impact of instruction set architecture on software development?

It influences the efficiency and complexity of programming needed for optimal performance.

What does the term 'hazard detection' refer to in pipelining?

Identifying conditions that may cause pipeline stalls or incorrect execution.

Explain why different CPU designs use varying instruction lengths.

To balance complexity with efficiency based on computational requirements.

How does clock rate influence CPU performance?

Higher clock speeds allow the execution of more instructions in a given timeframe.

What does changing cache sizes do to access times?

Larger caches may speed up access but can increase retrieval times if they're not well organized.

What types of multiprocessor systems are generally designed for high parallelism?

Symmetrical multiprocessing systems that allow equal resource access for all processors.

Describe the impact of instruction scheduling on pipeline performance.

Proper scheduling can enhance throughput and minimize stalls in the pipeline.

What challenges exist in between different CPUs sharing resources?

Resource contention can lead to delays and bottlenecks affecting overall system performance.

How can branch prediction affect CPU cycles?

By anticipating branching decisions, it reduces stalls and keeps the pipeline full.

What role does instruction scheduling play in reducing the execution time?

It organizes instructions to maximize parallel execution and minimize CPU idle time.

How are memory addresses structured in programs?

As sequential locations determined by the addressing scheme of the CPU.