WGU C952 Terms to Know | 209 ACCURATE DEFINITIONS | GUARANTEED PASS

Abstraction

Pulling out specific differences to make one solution work for multiple problems.

Active Matrix Display

A liquid crystal display using a transistor to control the transmission of light at each individual pixel.

Address

A value used to delineate the location of a specific data element within a memory array.

Address Translation (Address Mapping)

The process by which a virtual address is mapped to an address used to access memory.

AFR (Annual Failure Rate)

The estimated probability that a device or component will fail during a full year of use.

Aliasing

A situation in which two addresses access the same object; it can occur in the virtual memory when there are two virtual addresses for the same physical page

ALU (Arithmetic Logic Unit)

Hardware that performs addition, subtraction, and usually logical operations such as AND and OR.

AMAT (Average Memory Access Time)

A way of measuring the performance of a memory hierarchy configuration.

Amdahl's Law

A rule stating that the performance enhancement possible with a given improvement is limited by the amount that the improved feature is used. It is a quantitative version of the law of diminishing returns.

Assembler

A program that translates a symbolic version of instructions into the binary version.

Assembly Language

A symbolic representation of machine instructions.

Base Address

The starting address of an array in memory.

Base Register

A register that holds an array's base address.

Block (Line)

The minimum unit of information that can be either present or not present in a cache.

Blocking

A failure to retrieve information that is available in memory even though you are trying to produce it.

Can help to reduce cache miss rate.

Branch Instruction

An instruction that branches to an address and simultaneously saves the address of the following instruction in a register.

Branch not Taken (Untaken Branch)

A branch where the branch condition is false and the Program Counter (PC) becomes the address of the instruction that sequentially follows the branch.

Branch Taken

A branch where the branch condition is satisfied and the Program Counter (PC) becomes the branch target. All unconditional branches are taken branches.

Branch Prediction

A method of resolving a branch hazard that assumes a given outcome for the conditional branch and proceeds from that assumption rather than waiting to ascertain the actual outcome.

Branch Target Address

The address specified in a branch, which becomes the new Program Counter (PC) if the branch is taken. In LEGv8 architecture, the branch target is given by the sum of the offset field of the instruction and the address of the branch.

Cache Memory

A small, fast memory that acts as a buffer for a slower, larger memory.

Cache Miss

A request for data from the cache that cannot be filled because the data are not present in the cache.

CGM (Coarse-Grained Multithreading)

A version of hardware multithreading that implies switching between threads only after significant events, such as a last-level cache miss.

CPI (Clock Cycles per Instruction)

Average number of clock cycles per instruction for a program or program fragment.

Clock Period

The length of each clock cycle.

CMOS (Complimentary Metal Oxide Semiconductor)

Dominant technology for integrated circuits.

Combinational Element

An operational element, such as an AND gate or an ALU.

Compare and Branch on Zero (CBZ)

An instruction that compares the value in a register with zero and conditionally branches to a label if the comparison is equal.

Compiler

A computer program that translates high-level language statements into machine language instructions.

Context Switch

A changing of the internal state of the processor to allow a different process to use the processor that includes saving the state needed to return to the currently executing process.

Control

The component of the processor that commands the datapath, memory, and I/O devices according to the instructions of the program.

Control Hazard (Branch Hazard)

When the proper instruction cannot execute in the proper pipeline clock cycle because the instruction that was fetched is not the one that is needed; that is, the flow of instruction addresses is not what the pipeline expected.

Control Signal

A signal used for multiplexor selection or for directing the operation of a functional unit; contrasts with a data signal, which contains information that is operated on by a functional unit.

CPU (Central Processing Unit)

A processor, the active part of the computer, which contains the datapath and control and which adds numbers, test numbers, signals I/O devices to activate, and so on.

CPU Execution Time (CPU Time)

The actual time the CPU spends computing for a specific task.

CPU Performance (System Performance)

Elapsed time on an unloaded system and CPU performance to refer to user CPU time.

Data Hazard (Pipeline Data Hazard)

When a planned instruction cannot execute in the proper clock cycle because data that is needed to execute the instruction are not yet available.

Data-level Parallelism

Parallelism achieved by performing the same operation on independent data.

Datapath

The component of the processor that performs arithmetic operations.

Datapath Element

A unit used to operate on or hold data within a processor. In the LEGv8 implementation, the datapath elements include the instruction and data memories, the register file, the ALU, and adders.

Deasserted

The signal is logically low or false.

Destination Register

A register that receives the result of an operation.

Die (Chips)

The individual rectangular sections that are cut from a wafer, more informally known as chips.

Direct-mapped Cache

A cache structure in which each memory location is mapped to exactly one location in the cache.

Double Precision

A floating-point value represented in a 64-bit doubleword.

DRAM (Dynamic Random Access Memory)

Memory built as an integrated circuit; it provides random access to any location. Access time are 50ns and cost per gigabyte in 2012 was $5 to $10.

Edge-triggered Clocking

A clocking scheme in which all state changes occur on a clock edge.

ELR (Exception Link Register)

Holds the exception return address.

Error Detection Code

A code that enables the detection of an error in data, but not the precise location and, hence, correction of the error.

Exception (Interrupt)

An unscheduled event that disrupts program execution; used to defect overflow.

Exception Enable (Interrupt Enable)

A signal or action that controls whether the process responds to an exception or not; necessary for preventing the occurrence of exceptions during intervals before the processor has safely saved the state needed to restart.

Fanout

The number of transistors connected to an output

Fault Avoidance

Prevent faults from being introduced into the software.

Fault Forecasting (Predicting)

Predicting when a fault will occur in a system.

Fault Tolerance

The ability of a system to continue operating properly in the event of a failure.

FGC (Fine-grained Multithreading)

A version of hardware multithreading that implies switching between threads after every instruction.

5 Components of a Computer

input, output, memory, datapath, control

5 Pipelines Stages

5 Instructions will be in execution during any single clock cycle:

1. IF - Instruction Fetch

2. ID - Instruction Decode and Register File Read

3. EX - Execution or Address Calculation

4. MEM - Data Memory Access

5. WB - Write Back

Flash Memory

A nonvolatile semiconductor memory. It is cheaper and slower than DRAM but more expensive per bit and faster than magnetic disks.

Access times are about 5 to 50ms and cost per gigabyte in 2012 was $0.75 to $1.00

Forwarding ( Bypassing)

A method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer-visible registers or memory.

Frame Buffering

A portion of RAM containing a bitmap that drives a video display. It is a memory buffer containing a complete frame of data.

Frame Pointer

A value denoting the location of the saved registers and local variables for a given procedure.

Fully Associative Cache

A cache structure in which a block can be placed in any location in the cache.

Fully Connected Network

A network that connects processor-memory nodes by supplying a dedicated communication link between every node.

Global Miss Rate

The fraction of references that miss in all levels of a multilevel cache.

GPU (Graphics Processing Unit)

A hardware component that accelerates graphics.

Hardware Multithreading

Increasing utilization of a processor by switching to another thread when one thread is stalled.

Hexadecimal

A base-16 number system that uses sixteen distinct symbols 0-9 and A-F to represent numbers from 0 to 15.

Hierarchy of Memories

Architects have found that they can address conflicting demands of fast, large, and cheap memory with a hierarchy of memories, with the fastest, smallest, and most expensive memory per bit at the top of the hierarchy and the slowest, largest, and cheapest per bit at the bottom.

High-level Programming Language

A portable language such as C, C++, Java, or Visual Basic that is composed of words and algebraic notation that can be translated by a compiler into assembly language.

Hit Rate

The fraction of memory accesses found in a level of the memory hierarchy.

Hit Time

The time required to access a level of the memory hierarchy, including the time needed to determine whether the access is a hit or a miss.

Hot Swapping

Replacing a hardware component while the system is running.

Hypervisor (VMM/ Virtual Machine Monitor)

a type of computer software, firmware or hardware that creates and runs virtual machines (VMs).

ID (Instruction Decode)

Pull apart the instruction, set up the operation in the ALU, and compute the source and destination operand addresses.

IF (Instruction Fetch)

Move instruction from memory to the control unit

Imprecise Interrupt/ Imprecise Exception

Interrupts or exceptions in pipelined computers that are not associated with the exact instruction that was the cause of the interrupt or exception.

Instruction Format

A form of representation of an instruction composed of fields of binary numbers.

Integrated Circuit (Chip)

A device combining dozens to millions of transistors

Interrupt

An exception that comes from outside of the processor. (Some architectures use the term interrupt for all exceptions.)

Inverted Page Table

A page-table scheme that has one entry for each real physical page frame in memory; the entry maps to a logical page (virtual address) value.

IPC (Instructions Per Clock Cycle)

a measure of the performance of a central processing unit (CPU). A higher IPC means that the CPU can execute more instructions per second, which can lead to better performance.

Ex : A processor executes on average 2 instructions per clock cycle, then it has an IPC of 2 and CPI of 0.5

ISA (Instruction Set Architecture)

An abstract interface between the hardware and the lowest-level software that encompasses all the information necessary to write a ML program that will run correctly, including instructions, registers, memory access, I/O, and so on.

Latency (Pipeline Latency)

The number of stages in a pipeline or the number of stages between two instructions during execution

Least Significant Bit

The rightmost bit in an LEGv8 doubleword.

Load

The data transfer instruction that copies data from memory to a register

Load Use Data Hazard

A specific form of data hazard in which the data being loaded by a load instruction has not yet become available when it is needed by another instruction.

Loader

A systems program that places an object program in main memory so that it is ready to execute.

Local Miss Rate

The fraction of references to one level of a cache that miss; used in multilevel hierarchies.

Lock

A synchronization device that allows access to data to only one processor at a time.

LRU (Least Recently Used)

A replacement scheme in which the block replaced is the one that has been unused for the longest time.

Machine Language

A binary representation of machine instructions.

Magnetic Disk (Hard Disk)

A form of nonvolatile secondary memory composed of rotating platters coated with a magnetic recording material.

Main Memory (Primary Memory)

Memory used to hold programs while they are running; typically consists of DRAM in today's computers.

Mask

A bit pattern in conjunction with AND, since mask conceals some bits.

MEM (Memory)

The storage area in which programs are kept when they are running and that contains the data needed by the running programs

Message Passing

Communicating between multiple processors by explicitly sending and receiving information.

MIMD ( Multiple Instruction, Multiple Data Stream)

A multiprocessor

Mirroring

Writing identical data to multiple disks to increase data availability

Miss Penalty

The time required to fetch a block into a level of the memory hierarchy from the lower level, including the time to access the block, transmit it from one level to the other, insert it in the level that experienced the miss, and then pass the block to the requestor.