c952 computer architecture

Register File

state element with registers that can be R/W by supplying a register number

machine language

binary-coded instructions used by the computer

system software

programs that allow computer's hardware & software to work together

operating system

software that controls the execution of computer programs

Assembly Language

symbolic representations of machine code

IBM 360/91

Introduced dynamic detection of memory hazards, generalized forwarding, and reservation stations. Tomasulo's algorithm

Dynamic Random Access Memory (DRAM)

Memory built as an integrated circuit; it provides random access to any location. Access times are 50 nanoseconds and cost per gigabyte in 2012 was $5 to $10.

frame buffering

portion of RAM containing a bitmap that drives a video display

Datapath

processor component that performs arithmetic operations

Control

processor component that commands the datapath, memory, and I/O devices

Integrated circuit

aka chip - has millions of transistors.

Central processor unit (CPU)

aka processor. The active part of the computer, which contains the datapath and control and which adds numbers & other things

Static random access memory (SRAM)

memory built as an integrated circuit, but faster and lighter than DRAM.

Instruction set architecture

aka architecture. abstract interface between the hardware and the lowest-level software that has info to write a machine language program

Application binary interface (ABI)

user instruction set plus the OS interfaces used by application programmers

Volatile memory

Storage, such as DRAM, that retains data only with power.

Nonvolatile Memory

memory that retains data w/o power.

Magnetic disk

aka hard disk. nonvolatile secondary memory composed of rotating platters coated with a magnetic recording material.

access times are about 5 to 20 milliseconds and cost per gigabyte in 2012 was $0.05 to $0.10 It is widely used for data storage in computers due to its large capacity and relatively low cost.

Main memory

primary memory used to hold programs while they are running; has DRAM

Secondary memory

Nonvolatile memory used to store programs and data between runs; has flash

Flash memory

nonvolatile semiconductor memory. It is cheaper and slower than DRAM but more expensive per bit and faster than magnetic disks. Access times are about 5 to 50 microseconds and cost per gigabyte in 2012 was $0.75 to $1.00.

Single Instruction Single Data (SISD)

uniprocessor

Multiple Instruction Multiple Data (MIMD)

multiprocessor

Single Program, Multiple Data Streams (SPMD)

MIMD programming model, where a single program runs across all processors.

Single Instruction Stream, Multiple Data Streams (SIMD)

same instruction applied to many data streams

Data-level parallelism

Parallelism achieved by performing the same operation on independent data

LEGv8

assembly instructions

multimedia extensions (MMX)

instruction set supported by a processor that has multimedia-specific functions.

data hazard (pipeline data hazard)

when inst. cannot execute in the proper clock cycle because data is unavailable.

forwarding (bypassing)

resolves data hazard by retrieving the missing data element from internal buffers

Structural hazard

when instr. cannot execute in the proper clock cycle because the hardware does not support instr.

Pipelining

allows CPU to work on more than one instruction at a time. Formula
total process time = [longest task * (total load -1)] + total load time

R-format ALU operations

Requires register file and the ALU.

Program Counter (PC)

register that contains the address of the next instruction

output

results of the operation of any system

temporal locality

if a data location is referenced then it will tend to be referenced again soon

spatial locality

if a data location is referenced, data locations with nearby addresses will tend to be referenced soon

Memory hierarchy

uses multiple levels of memories; as the distance from the processor increases, the size & access time of the memories both increase.

Block (or line)

minimum unit of info

Hit rate

The fraction of memory accesses found in a level of the memory hierarchy.

Miss rate

The fraction of memory accesses not found in a level of the memory hierarchy

miss penalty

The time required to fetch a block into a level of the memory hierarchy from the lower level, including the time to access the block, transmit it from one level to the other, insert it in the level that experienced the miss, and then pass the block to the requestor.

Hit time

The time required to access a level of the memory hierarchy, including determining if access is a hit or a miss.

Parallelization

divide program into separate components that run in parallel on individual computers

superscalar

associated with hardware

ARM architecture

supports 16-bit

Amdahl's Law

formula used to find the maximum improvement possible by improving a particular part of a system. In parallel computing, Amdahl's law is mainly used to predict the theoretical maximum speedup for program processing using multiple processors

multiprocessor

computer w/ 2+ CPUs

Uniform Memory Access (UMA)

A multiprocessor in which latency to any word in main memory is about the same no matter who requests access

Non-Uniform Memory Access (NUMA)

Varying system memory access times

loop unrolling

A technique to get more performance from loops that access arrays, when multiple copies of the loop body are made

Blocking

can help reduce cache miss rate…. a failure to retrieve information that is available in memory even though you are trying to produce it

Set Associative Cache

cache w/ fixed number of locations (at least two) where each block can be placed.

RAID 0 (Disk Striping)

Disk Striping

2+ drives needed
no data redundancy
If one drive fails, all data is lost.

RAID 1 (mirroring)

Two drives are used in unison. if one drive fails, the other is a copy

RAID 2

Bit-level striping. dedicated Hamming-code parity. OBSOLETE.

RAID 3

Byte-level striping. dedicated parity
OBSOLETE, replaced with RAID 5.

raid 4

dedicated parity
replaced with RAID 5

Block-level striping

RAID 5

Disk striping with parity
3+ disks
fault tolerance

RAID 6

Disk striping with parity
4+ disks
fault tolerance
can survive the failure of two drives

silicon crystal ingot

silicon crystal rod that is between 8 and 12 inches in diameter and about 12 to 24 inches long.

wafer

silicon ingot slice no more than 0.1 inches thick, used to create chips.

Transistor

on/off switch controlled by an electric signal

very large-scale integrated (VLSI) circuit

has one to millions of transistors

silicon

natural semiconductor

1. Excellent conductors & insulators of/from electricity

3. can conduct or insulate under special conditions (as a switch)

Semiconductor

can conduct electricity under some conditions

Die

rectangles cut from a wafer, aka chips.

complementary metal-oxide semiconductor (CMOS)

tech for integrated circuits

LEGv8 word

natural unit of access in a computer, 32 bits

LEGv8 doubleword

natural unit of access in a computer, 64 bits (8 bytes)

LEGv8 register

64 bits wide

Smaller is faster

large number of registers may increase the clock cycle time simply because it takes electronic signals longer when they must travel farther.

Data transfer instruction

command tht moves data between memory and registers

Address

value used to delineate specific data element location in a memory array

load

data transfer instruction that copies data from memory to a register

LEGv8 LDUR

constant portion of the instruction + contents of the 2nd register = memory address

base address

starting address of an array in memory (5000 below)

base register

register that holds an array's base address (X22 below)

offset

value added to a base address to locate a particular array element (8 below)

Big Endian

cpu/memory architecture in which the most significant byte is stored at the lowest memory address.

store register

instruction complementary to load. copies data from register to memory.

LEGv8 STUR

store register

spilling register

process of storing less frequently used variables into memory

reservation station

buffer that holds the operands and the operation

commit unit

unit in a dynamic or out-of-order execution pipeline that decides when it is safe to release operation results

Reorder Buffer

buffer that holds results in a dynamically scheduled processor until it is safe to store results

out-of-order execution

when an instruction blocked from executing does not cause the following instructions to wait

in-order commit

commit where the results of pipelined execution are written in the same order that instructions are fetched

VLIW

instruction set architecture that launches many independent operations in a single wide instruction

ARMv8 virtual memory

64-bit addressed. The upper 16 bits are not used, so only 48 bits are used

address translation (address mapping)

the process by which a virtual address is mapped to an address used to access memory

Exception Syndrome Register (ESR)

record the cause of the exception

FADDS, FSUBS

Single-precision arithmetic

FADDD, FSUBD, FMULD, FDIVD

Double-precision arithmetic

FCMPS, FCMPD

Single- and double-precision comparison

motivations for virtual memory

1. safely share memory among several programs

2. remove burdens of limited amount of main memory

2. allow single user program to exceed the size of primary memory

virtual memory

uses main memory as a "cache" for secondary storage

physical address

An address in main memory.

Protection

ensures that multiple processes sharing the processor, memory or I/O devices cannot interfere with one another by reading or writing each other's data

page

a virtual memory block