computer science 1.1

what is the processor/CPU

• ‘brain’ of the computer

• executed instructions

• which allows programs to run

ALU

• completes all arithmetic and logical operations

• boolean logic operations = AND/OR/

CU

• sends signals to control/coordinate activities of the CPU

• manage flow of data between CPU and other devices

• accepts next instr

• decodes instr

• storing resulting data back in memory

registers

• temporary storage location

• inside the CPU

• used for a single specific purpose

• fasted access speed than RAM / secondary storage

PC

• holds the address

• of the next instr to be executed

• contents copied to the MAR at the start of the FDE

• increments vy one every cycle

accumulator (ACC)

• holds inputs/outputs

• holds results from calculations

• from the ALU

• stors data which has come from MDR/RAM

memory address register (MAR)

• holds the address of a location

• to be read/written to

memory data register (MDR)

• temporarily stores data

• that HAS BEEN read/

• data that needs to be written

current instruction register (CIR)

• holds the current instruction

• being executed

• divided into operand and opcode

buses

• set of parallel wires

• connect two or more components inside the CPU

• data, control, address = system bus

data bus

• bi-directional bus

• transmits data between the CPU and memory mate

address bus

• used to transmit the memory addresses

• which specify where data is to be sent to / retrieved from

c

control bus

• bi-directional bus

• used to transmit control signals

• to coordinate CPU operations

operand

• contains data or address of the data

• that the operation will be performed

opcode

• specifies the type of instr

• to be executed

pipelining

• concurrent processing of multiple instructions

• allows the next instr to be fetched whilst previous is decoded

• increases no. instr processed in a set period of time (so increased speed of execution)

• prevents CPU having to wait

• prevents idle components

fetch

• Address from the PC is copied to the MAR

• Instruction held at that address is copied to MDR by the data bus

• Simultaneously, the contents of the PC are incremented by 1

• The value held in the MDR is copied to the CIR

decode

• contents of CIR splits into operand and opcode

execute

• decoded instr is executed

3 factors which affect CU performance

1. clock speed

2. no. cores

3. cache memory

4. (RAM)

clock speed

• the speed at which the fde cycle is completed

• higher the speed the more data/instr executed within a given time

core?

• an independent processor

• that is able to run its own fetch-execute cycle

number of cores

• a computer w/ multiple cores will execute more than one fde cycle

• at one time

• so more instr are executed at once

• BUT not all programs will be able to utilise multiple cores

cache memory

• cache memory is very quick access memory that stores frequently used instr/programs

• quicker to access than the RAM

• memory that is closer to the CPU

• improving CPU performance

cache levels 1-3

• level 1- Very fast memory cells with a small capacity. (2-64KB)

• level 2- Relatively fast memory cell, with a medium sized capacity. (256KB-2MB)

• level 3- Much larger and slower memory cell.

von neumann architecture

• uses one physical piece of memory for data/instr

• uses same bus for instructions and data

• can only read/write data or instr

NOT BOTH at the same time

harvard architecture

• separate memory blocks for instr and data

• different sets of buses, one for instr and one for data

• can read/write data and instr simultaneously

• instruction memory stored in ROM

• commonly in embedded

• useful when memories have different characteristics (instr = read-only, but data = read-write)

• allows you to optimise size of memory e..g instr memory designed as larger

advantages of von Neumann

• cheaper to develop, CU is easier to design (less complex)

• programs can be optimised in size

advantages of Harvard architecture

+quicker execution, as data and instr fetched in parallel, requires two buses (more complex)

-development is more expensive

• memories can be different sizes. can make more efficient use of space

contemporary processing

• make use of both von Neumann and Harvard architectures

• von Neumann: used when working with data and instr in main memory

• Harvard: used to divide cache into instr cache and data cache

how does pipelining improve performance of the CPU

components

why do computer systems store data in binary

• computers use binary logic- on/off, 1/0

• they’re based on switches and transistors

• binary is high tolerance

RAM

• volatile , meaning that data is lost once the power is switched off

• used for storing programs and data and parts of OS currently in use

• 
  

ROM

• non-volatile , retains data when power switched off

• used for storing BIOS / bootstrap instructions

• is read-only