Computer Architecture and Organization Prelim 2

Computer architecture

Defines the details of how a set of software and hardware technology standards interact to form a computer system, also known as a platform.

System Design

This type of computer architecture involves all the hardware components of a system, such as the central processing unit (CPU) and memory controllers.

Instructional Set Architecture

This type of computer architecture involves the embedded programming language of a CPU, which defines its functions and capabilities.

Microarchitecture

This is also known as computer organization.

Von Neumann Architecture

A good example of computer architecture. Numerous general-purpose computers, up until today, utilize this architectural design.

x86 architecture

The term x86 architecture pertains to a microprocessor that has the capability to execute a 32-bit instruction set.

Emu8086

A prevailing offline emulator of Intel 8086 microprocessor with 8086 assembler, which is also compatible with Advanced Micro Devices (AMD), disassembler, source editor, and an emulator with debugger.

Emulator

Runs programs on Virtual PC. This completely blocks a program from accessing real hardware since the assembly code runs on a virtual machine, which makes debugging easier.

Label

This may subsequently be used as an address or as data in another instruction's address.

Mnemonic

This is the name of the operation or function of the assembly language statement which may correspond to any of the following: Machine instructions, Assembler directives, Macro Definition.

Machine instructions

These are executable instructions that instruct the processor what to do. Note that each executable instruction generates one machine language instruction. These are also known as operational codes or opcodes.

Assembler directives

These non-executable commands direct the assembler about the various aspects of the assembly process. These do not generate machine language instructions

Macro Definition

It is a section of code that programmers write once, and can be used many times. It encompasses a text substitution mechanism that is handled by the assembler at assembly time.

Operand

This identifies an immediate value, a register value, or a memory location. Generally, assembly language provides conventions to distinguish the type of operand, as well as the conventions for indicating the addressing mode.

Comment

This begins with a semicolon ( ; ) which signals the assembler that the rest of the line is a comment and must be ignored by the assembler. Comments can occur at the right-hand side of an assembly statement or occupy an entire text line.

Registers

The processor includes some internal memory storage locations known as registers which do not require memory access. Note that a number of registers are already built into a processor chip.

General-purpose registers

May contain the operand for any opcode, which can be assigned to a variety of functions. In some cases, their use within the instruction set is orthogonal to the operation.

AX

Primary accumulator – used for input/output (I/O) operations and in most arithmetic instructions.

BX

Base register – used in indexed addressing

CX

Counter register – stores the loop count in iterative operations.

DX

Data register – used in I/O operations and for multiplying and dividing large values.

IP

Instruction pointer – stores the offset address of the next instruction to be executed.

SP

Stack pointer – provides the offset value within a program stack.

BP

Base pointer – used in referencing parameter variables passed to a subroutine.

SI

Source index – used as source index for string operations.

DI

Destination index – used as destination index for string operations.

Control registers

Contain bits that manage the operation of the floating-point unit including the type of rounding control (single, double, or extended precision), and bits to enable or disable exception conditions.

CR0

This contains the control flags that manage the operating mode and status of the processor.

OF

Overflow Flag – indicates the overflow of a high-order bit of data after a signed arithmetic operation.

DF

Direction Flag – determines the direction (left or right) for moving or comparing string data. DF is 0 if the string operation direction is left to right. DF is 1 if the string operation direction is right to left.

IF

Interrupt Flag – enables or disables external interrupts. When IF is set to 0, the external interrupt is disabled. When IF is set to 1, the external interrupt is enabled.

TF

Trap Flag – sets the operation of the processor to single-step mode.

SF

Sign Flag – shows the sign of the result of an arithmetic operation, indicated by the leftmost bit. A positive (+) result is denoted by 0. A negative (-) result is denoted by 1.

ZF

Zero Flag – indicates the result of an arithmetic or comparison operation. A non-zero result is denoted by 0. A zero result is denoted by 1.

AF

Auxiliary Carry Flag – contains the carry of an arithmetic operation from bit 3 to bit 4.

PF

Parity Flag – involves the total number of 1-bit in the result of an arithmetic operation. If the total number of 1-bit is even, PF is 0. If the total number of 1-bit is odd, PF is 1.

CF

Carry Flag – contains the carry of 0 or 1 from a high-order bit after an arithmetic operation.

CR1

This is a reserved control register.

CR2

This involves the page fault linear address.

CR3

This enables the processor to translate a linear address into physical address by locating the page directory and page tables for the current operation.

Segmentation

Used to define logical memory partitions subject to access controls. This process is performed to enhance the speed of fetching data from the memory and easily execute instructions in a computer system.

Segments

Also known as memory segments, are specifically defined areas in a program for containing instruction codes, data elements, or program stacks.

Code memory segment

he size of this memory section is determined before a program runs. It contains all the instructions to be executed.

Data memory segment

This contains the data elements that can be used in the program. In an assembly program, this segment can be identified through the following sections: .data, .bss

.data

This section is commonly used to declare data memory segments that remain static throughout the program.

.bss

This section contains buffers for future data declaration during the program execution.

Stack memory segment

This holds the data and return addresses of procedures or subroutines in a program.

Segment registers

Work together with general-purpose register to access any memory value.

CS

Code segment register – denotes the segment that holds the instruction being executed. A 16-bit CS register stores the starting address of the code memory segment.

DS

Data segment register – specifies the segment containing the data, the constant, or the work area for a program. A 16-bit DS register stores the starting address of the data memory segment.

SS

Stack segment register – refers to the segment that contains a user-visible stack. A 16-bit SS register stores the starting address of the stack.

ES

Extra segment register – is a spare segment register that may be utilized for storing data.

Offset

Stored as part of the instruction set. It usually represents the number of address locations added to a base address in order to obtain specific addresses.

Nibble

4-bit

Byte

8-bit

Word

16-bit

Doubleword

32-bit

Quadword

64-bit

Double Quadword

128-bit

Integer

A signed binary value contained in a byte, word, or doubleword using 2's complement representation.

Ordinal

An unsigned integer contained in a byte, word, or doubleword.

Packed Binary Coded Decimal (BCD)

A representation of a BCD digit wherein two (2) digits are stored per byte (8-bit). The value of the decimal digit is within the range of 0 to 99.

Unpacked Binary Coded Decimal (BCD)

A representation of a BCD digit wherein one (1) digit is stored per byte (8-bit). The value of the decimal digit is within the range of 0 to 9.

Near Pointer

This contains a 16-bit offset addressing information from the current segment.

Far Pointer

This contains a 32-bit of addressing information which is composed of a 16-bit segment register value and a 16-bit offset value.

Bit Field

It is a continuous sequence of bits in which the position of each bit is considered as an independent unit. It can begin at any bit position of any byte and can contain up to 32 bits.

Bit String

It is a continuous sequence of bits containing zero (0) up to the number of bits in the string less one. It is commonly used to represent sets or to manipulate binary data.

Floating Point

It is a data type that encompasses decimal points that are not considered as fixed point numerals.

Packed Single Instruction-Multiple Data (SIMD)

This is a set of data types that were introduced to the x86 architecture as part of the extensions of the Intel 8086 instruction set to optimize the performance of multimedia applications.

Addressing Modes

This pertains to the way in which the operand of an instruction is specified. The information contained in the instruction set can either be the value of the operand or the address of the operand or result.

Mode field

This determines which addressing mode is to be used. Note that, one (1) or more bits in the instruction format can be used as a mode field.

Effective address

In a system without any virtual memory (VM), this can either be the main memory address or a register. For computers with VM, the effective address is a virtual address or a register.

Memory management unit

This performs the actual mapping of a physical address that is not visible to programmers.

Immediate addressing

This is the simplest addressing mode wherein the operand is an immediate value stored explicitly in the instruction. This mode can be utilized to define and use constants or set initial values of variables.

Direct memory addressing

This requires only one (1) memory reference and no special calculations needed. The address field contains the effective address of the operand. Earlier generations of computers commonly utilize this mode, but modern computer architectures rarely apply this mode.

Indirect memory addressing

This mode encompasses an address field referring to an address of a word in memory, which in turn contains a full-length address of the operand.

Register addressing

This mode involves an address field referring to a register containing the operand. An address field that references registers has 3 to 5 bits, thus a total of eight (8) to 32 general-purpose registers can be referenced.

Register indirect addressing

In this mode, the address of the operand is placed in a register. The address space limitation of the address field is overcome by having a field referring to a word-length location containing an address.

Displacement addressing

This is considered a very powerful mode of addressing since it has the combined capabilities of direct memory addressing and register indirect addressing.

Stack addressing

This mode is a form of implied addressing. The machine instructions need not include a memory reference, but implicitly operate on a stack that is a linear array of locations

Instruction Format

An instruction format defines the layout of the bits of an instruction, in terms of its constituent fields. It is composed of an opcode, zero or more operands (implicit or explicit), and the mechanism indicating the addressing mode used for each operand.

Instruction length

Or instruction format length, is the most basic design-related matter that can be encountered by programmers. Deciding the value for the instruction length affects, and is affected by, the memory size, memory organization, bus structure, processor complexity, and processor speed.

Complex Instruction Set Computer (CISC): Variable length instructions

A processor characterized with a rich instruction set providing a variety of features, such as the ability to load operands from memory, perform an operation, and store the result to memory, all in one instruction.

Reduced Instruction Set Computers (RISC): Fixed length instructions

A processor having fewer number of instructions that individually performs a simpler task. The reduction of instructional set complexity leaves more space for registers. This architecture is optimized to execute individual instructions at a very high speed