Module 6 ECE 2020

Combination logic

Block diagram for a decoder

Restriction on outputs

Only 1 at a time can be 1

**How is it decided which input will be 1

Binary values!!

Decoders with enablers

Truth table, decoder with enabler

Logic equations for the truth table before

Mixed logic implementation of the equations

Mixed logic 3 to 8 encoder

Implementing functions using decoders, minterms

Steps, using a decoder

Implementing F using a NOR gate

invert then use nor

why a 3-to-8 decoder can be built from two 2-to-4 decoders.

Visual, big encoder made by two smaller encoders

Another example of visual

What is the difference between a decoder and an encoder?

Why do we care about all zero line for decoders, but not for encoders?

Encoder truth table

Expression for the outputs of a decoder

Explain this

It means an encoder converts “which event happened?” into a binary number representing that event.

Explain this

Priority encoder truth table

explain this

explain this

Explain this

Behaviour of multiplexers

What is a multiplexer (MUX)

Difference between multiplexer, encoder, decoder

Explain the truth table, MUX

explain this

break this down

This page is moving from the ideal switch model of a 2-to-1 MUX to how that switch is physically built using CMOS transistors.

MUX with PDN and PUN

The main point is:

A CMOS transmission gate is used as the physical switch inside the MUX

Explain

Explain method 1

Method 1 builds a 4-to-1 MUX by cascading three 2-to-1 MUXes, with each MUX implemented using transmission gates.

“Cascade” means the output of one stage becomes an input to the next stage.

Stage 1 method 1

Stage 2 method 1

explain this to me - step 1

Step 2, method 2

Explain this

Method 3 visual

1×4 DeMux

Visual DEMUX

What is the big block in the middle doing?

break ts down

Look → A2 is acting as an enabler!

More about how a multiplexer works

What is a demultiplexer useful for?

Adders and half adders

Tell me more about adders and half adders.

Logic equations, adders and half adders

Full adder operation

Full adder equations

Multi bit addition

Mainly relies on chain full adders

Adders, set up with logic gates

Property of a half adder

Graphic for a full adder

What are the truth tables for a half adder?

Full adder TT?

Sum expression, full adder

Expression for Cout, full adder

Full adder drawn as 2 half adders

Explain this, part 1

explain this, part 2

Now explain the explanation, in more detail

See module 6 notes for a better explanation

What is this tryna say

how bout this

what is this tryna say?

What is a twos compliment?