WEEKS 1-5

Clock Skew

The difference in arrival times of the clock signal at different components due to manufacturing variances and signal propagation delays.

Clock Jitter

Variability in the timing of clock edges due to noise and variations in power supply, leading to uncertainty in signal timing.

Flip-Flop

An edge-triggered device that samples and captures data on the rising edge of a clock signal.

Latch

A level-sensitive device that follows the input signal as long as the enable signal is active.

Setup Time (Tsu)

The minimum time before the clock edge that the data input must be stable.

Hold Time (Thold)

The minimum time after the clock edge that the data input must remain stable.

Propagation Delay (tpd)

The time between a change at the input and the corresponding change at the output.

Contamination Delay (tcd)

The minimum time it takes for an output to start changing after the input changes.

Phase Locked Loop (PLL)

A technology used to synchronize clock phases with a reference, potentially multiplying the frequency.

Delay Locked Loop (DLL)

A technology that introduces specific delays to synchronize clock signals across different systems.

Metastability

A state where a flip-flop output is neither in a clear high nor low state, occurring during data transitions.

Clock Distribution

The mechanism that distributes the clock signal to various components to ensure synchronous operations.

Timing Analysis

The process of assessing the timing behavior of signals in digital circuits, focusing on delays and synchronization.

Separation of Cycles

The ability to distinguish between different operational cycles in a synchronous system.

Synchronous System

A system where operations are coordinated by a clock signal to ensure proper timing and sequencing.

Clock Gating

A technique to reduce power consumption by disabling the clock to portions of the circuit when not needed.

Useful Skew

Clock skew that can be exploited to reduce timing violations and improve setup and hold times.

Sequential Logic

Logic circuits in which the output depends on the current and previous inputs, introducing memory elements like latches and flip-flops.

CMOS Transistors

Fabricated on silicon wafers using processes like lithography, deposition, and etching.

Lithography Process

The mainstream chip manufacturing process, similar to a printing press, used to transfer patterns from a mask to a wafer.

Silicon Wafers

Round silicon disks that serve as the substrates for all CMOS fabrication, with precise control of crystal structure.

p-type Substrate

The base material, typically silicon, used for nMOS transistors in CMOS fabrication.

n-well

A doped region in the p-type substrate required for the body of pMOS transistors.

SiO2 (Silicon Dioxide)

An insulating layer, also known as oxide, used as a protective layer, gate dielectric, and field oxide in CMOS fabrication.

Polysilicon

A layer of many small silicon crystals deposited on the gate oxide, heavily doped to be a good conductor and often used as gate material.

n+ Diffusion

Heavily doped n-type regions forming the source, drain, and n-well contacts for nMOS transistors.

p+ Diffusion

Heavily doped p-type regions forming the source, drain, and substrate contacts for pMOS transistors.

Substrate Tap

A heavily doped p+ region in the p-substrate to tie the substrate to GND, avoiding a Schottky Diode.

Well Tap

A heavily doped n+ region in the n-well to tie the n-well to VDD, avoiding a Schottky Diode.

Mask

A patterned template used in lithography to imprint optical patterns onto a layer of photoresist on the wafer.

Oxidation

A fabrication step where SiO2 is grown on top of a silicon wafer, typically at high temperatures with H2O or O2.

Photoresist

A light-sensitive organic polymer spun onto the wafer, which softens or hardens upon exposure to light, enabling pattern transfer.

Etch

The process of removing unwanted material (e.g., oxide with hydrofluoric acid or using plasma) to define features.

Ion Implantation

A doping technique where a beam of ions is blasted at the wafer to introduce dopants into exposed silicon at controlled depths.

Self-Aligned Process

A technique using an existing feature (like the polysilicon gate) to block dopants and automatically align subsequent diffusion regions.

Chemical Vapor Deposition (CVD)

A process for depositing thin films (e.g., polysilicon) onto the wafer by reacting gases in a furnace.

Field Oxide

A thick insulating layer of oxide that covers the chip surface and isolates devices from each other.

Contact Cuts

Openings etched through the insulating oxide layers to allow metal interconnects to connect to underlying doped silicon regions.

Metalization

The process of depositing a metal layer (e.g., aluminum or copper) over the wafer and patterning it to form interconnect wires.

Strained Silicon

A technology that applies tensile or compressive strain to silicon to increase electron and hole mobility, leading to faster switching and higher current.

High-k Dielectric

A gate dielectric material with a high dielectric constant, used to reduce leakage current, improve gate control, and enhance scalability in transistors.

Low-k CDO Dielectric

A carbon-doped oxide dielectric material with a low dielectric constant, used between copper interconnect layers to reduce capacitance and improve performance.

FinFET (Tri-Gate Transistor)

A 3-D transistor geometry where the conducting channel wraps around a vertical silicon fin, enabling better gate control, higher drive current, and reduced leakage compared to planar transistors.

Planar Transistor

Traditional 2-D transistors that form a conducting channel on the flat silicon surface under a gate electrode.

Gate-All-Around (GAA) Transistors

Advanced transistor structures, sometimes called RibbonFET or MBCFET, where the gate wraps around the entire channel, which can be stacked in nanosheets or ribbons.

Magnetoresistive RAM (MRAM)

A non-volatile memory technology under development that uses magnetic states to store information, offering data retention without power.

Dopants

Impurities (e.g., Boron for p-type, Arsenic or Phosphorus for n-type) introduced into silicon to create p-type (holes) or n-type (electrons) regions.

Diffusion (Doping method)

A doping process where dopants are introduced into silicon from a gas or solid source at high temperatures, causing them to spread within the crystal lattice.

RC Delay

The propagation delay influenced by the resistance of interconnects and the capacitance of wiring, affecting overall circuit speed.

Drive Current

The amount of current a transistor can deliver, which is crucial for switching speed and signal propagation in circuits.

Leakage Current

Unwanted current that flows through a transistor when it is ideally in the off state, leading to power consumption.

DeMorgan's Theorem

A set of rules for converting AND/OR logic to their equivalent NAND/NOR forms, expressed as (AB)’ = A’+B’ and (A+B)' = A’B', along with their inverted forms.

Bubble Pushing

A technique used to convert logic networks between AND/OR gates to NAND/NOR and inverters, simplifying logic by visually moving negation bubbles.

Static CMOS Circuits

CMOS circuits that use N and P channel networks to implement logic functions with fixed pull-up and pull-down networks, connecting the output to VDD or VSS. They are known for ease of design and absence of clocking.

Series network (CMOS)

A configuration of transistors in a CMOS circuit that implements an 'AND' function.

Parallel network (CMOS)

A configuration of transistors in a CMOS circuit that implements an 'OR' function.

Duality (CMOS)

The principle that N and P networks in CMOS circuits must implement complementary functions, ensuring that at most one network conducts for any given input to avoid short circuits.

Exclusive-NOR (XNOR) Gate

A logic gate whose output is true only if all its inputs are true or all its inputs are false (OUTPUT = AB + A’B’).

Pseudo nMOS Logic

A lightweight CMOS logic variant that typically lacks an explicit PMOS pull-up network, instead using a single NMOS pull-down with a weaker PMOS load or fixed transistor arrangement for pull-up behavior.

Strong 0 (nMOS)

The ability of nMOS transistors to pass a voltage close to GND effectively, making them ideal for pull-down networks.

Strong 1 (pMOS)

The ability of pMOS transistors to pass a voltage close to VDD effectively, making them ideal for pull-up networks.

Degraded 1 (nMOS)

A weakened logic '1' signal passed by an nMOS transistor, where the output voltage is reduced by the threshold voltage (VDD - Vtn).

Degraded 0 (pMOS)

A weakened logic '0' signal passed by a pMOS transistor, where the output voltage is increased by the threshold voltage (VSS + |Vtp|).

Transmission Gates

A pair of transistors (nMOS and pMOS) controlled by complementary signals, used to pass both logic '0' and '1' signals well, typically without degradation, unlike individual pass transistors.

Tristate Buffer

A buffer that can produce a high-impedance (Z) output state when disabled (EN=0), in addition to passing a '0' or '1' when enabled.

Multiplexer (Mux)

A logic device that chooses one of several input signals and forwards the selected input into a single output line, based on a set of select signals.

D Latch (Level-Sensitive Latch)

A sequential logic device that is 'transparent' (input D flows to output Q) when the clock (CLK) is high, and 'opaque' (Q holds its old value) when CLK is low.

D Flip-flop

A sequential logic device built from master and slave D latches that samples its input D on a clock edge and transfers it to the output Q, holding the value until the next clock edge.

MOS Capacitor

A fundamental structure in MOS devices consisting of a gate and body separated by an insulator (silicon dioxide), which can operate in accumulation, depletion, or inversion modes.

Accumulation (MOS)

An operating mode of a MOS capacitor where a negative gate voltage attracts holes to the gate-oxide interface in a p-type body.

Depletion (MOS)

An operating mode of a MOS capacitor where a moderate positive gate voltage repels holes, creating a region devoid of mobile carriers near the gate-oxide interface.

Inversion (MOS)

An operating mode of a MOS capacitor where a sufficiently positive gate voltage attracts minority carriers (electrons in a p-type body) to form a conducting channel at the gate-oxide interface.

Enhancement-mode nMOS

An nMOS transistor that is non-conducting when the gate-source voltage (Vgs) is 0, requiring a positive Vgs greater than the threshold voltage (Vt) to turn on.

Depletion-mode nMOS

An nMOS transistor that is conducting when the gate-source voltage (Vgs) is 0, requiring a negative Vgs to turn off.

Vgs

Gate-to-source voltage (Vg - Vs) in a MOS transistor.

Vgd

Gate-to-drain voltage (Vg - Vd) in a MOS transistor.

Vds

Drain-to-source voltage (Vd - Vs) in a MOS transistor.

Cutoff Region (nMOS)

The operating region of an nMOS transistor where Vgs < Vt, no channel forms, and the drain-source current (Ids) is approximately zero.

Linear Region (nMOS)

The operating region of an nMOS transistor where Vgs > Vt and 0 < Vds < Vgs - Vt, causing a channel to form and Ids to increase with Vds, behaving like a voltage-controlled resistor. Also known as Triode Region.

Saturation Region (nMOS)

The operating region of an nMOS transistor where Vgs > Vt and Vds > Vgs - Vt, causing the channel to pinch off near the drain and Ids to become largely independent of Vds, behaving like a current source.

pMOS Transistor

A MOS transistor where application of a negative gate voltage (relative to source) draws holes into the region below the gate, forming a p-type channel and allowing conduction due to holes.

Qchannel

The amount of charge in the channel of a MOS transistor, which can be modeled as the gate-oxide-channel capacitance (Cg) multiplied by the effective gate voltage (Vgc - Vt).

Carrier Velocity (v)

The speed at which charge carriers (electrons or holes) move through the channel of a MOS transistor, proportional to the lateral electric field between source and drain.

Electron/Hole Mobility (μ)

A material property that quantifies how quickly electrons or holes move in response to an electric field.

Beta (β) parameter

The transconductance parameter in MOSFET current equations, defined as μ * Cox * (W/L), which scales the current with carrier mobility, gate oxide capacitance per unit area, and transistor geometry (width and length).

PMOS mobility (μp)

The mobility of holes in a pMOS transistor, which is typically 2-3x lower than electron mobility (μn) for older technologies, meaning pMOS transistors often need to be wider to provide similar current.

Gate Capacitance (Cg)

The capacitance between the gate and the channel of a MOS transistor, which is crucial for forming the channel charge necessary for operation.

Diffusion Capacitance (Csb, Cdb)

Parasitic capacitance between the source (Csb) or drain (Cdb) and the body of a MOS transistor, arising from reverse-biased diodes, and dependent on area and perimeter.

Effective Resistance (R_on)

A simplification for MOSFET analysis where a transistor is treated as a resistor with a value R, averaged across the switching of a digital gate, used primarily to predict RC delay.

Unit nMOS

In an RC delay model, an nMOS transistor with a defined effective resistance R and capacitance C, used as a reference for sizing other transistors.

Unit pMOS

In an RC delay model, a pMOS transistor typically represented with an effective resistance of 2R and capacitance C, reflecting its lower mobility compared to a unit nMOS.

MOSFET (MOS Transistor)

Metal-Oxide-Semiconductor Field-Effect Transistors, which can be n-type (NMOS) or p-type (PMOS) and are used to implement switching between conducting and non-conducting states.

CMOS (Complementary Metal-Oxide-Semiconductor)

A technology that uses both PMOS and NMOS devices on the same circuit to implement logic with low static power consumption.

Dynamic CMOS

A CMOS logic style that uses clocks and often capacitors to store charge, offering faster switching and smaller area compared to static CMOS but requiring careful clocking and timing design.

Pull-Down Network (PDN)

In a CMOS gate, the network of NMOS devices that connects the output to ground (VSS) when the logic function is true, causing the output to go to a strong '0'.

Pull-Up Network (PUN)

In a CMOS gate, the network of PMOS devices that connects the output to VDD when the complement of the logic function is true, causing the output to go to a strong '1'.

AOI (AND-OR-Invert) Gate

A common compound CMOS gate that implements a logic function by performing AND operations, then an OR operation, followed by an inversion.

OAI (OR-AND-Invert) Gate

A common compound CMOS gate that implements a logic function by performing OR operations, then an AND operation, followed by an inversion.

XOR Gate

Exclusive OR logic gate, whose output is true if and only if its inputs differ (often used in arithmetic units).

Threshold Voltage (Vth)

The minimum gate-to-source voltage (VGS) required to create a conducting channel between the source and drain in an enhancement-mode MOSFET.