pipelining

How do I calculate the latency of a unpipelined implementation?

sum of all stages + pc register

How do I calculate the time for a unpipelined implementation to have an instruction retired?

the same as the latency of an unpiplined implementation

how do I calculate the throughout of a unpipelined and pipelined implementation

(1 / latency) * 10^12

latency of a pipelined implementation

register length * 5 + latency of unpipelined

retired latency of pipelined

longest processor time + 1 register