Revision Part-VII

Register

Which Part 08 structure should you think of first when a value must persist unchanged across clock cycles until explicitly updated?

Shift register

Which structure should you choose when information must be stored while its bit positions are deliberately changed across cycles?

Counter

Which structure is most natural when the machine must remember a numerical position or amount of progress?

Multiplexer

Which structure converts a control decision into the selection of one data source from several candidates?

Bus

Which structure conceptually groups related signals into a meaningful information-transport path?

Tri-state driver

Which structure can actively drive 0 or 1 or relinquish a shared physical line by entering Z?

Memory

Which storage organization is most appropriate when many similar words must be selected by numerical address rather than individually named?

Register = STORE; shift register = STORE + REPOSITION; counter = STORE + NUMERIC PROGRESS; MUX = SELECT/ROUTE; bus = TRANSPORT; tri-state = SHARED-LINE OWNERSHIP; memory = ADDRESSABLE STORE.

What compact map summarizes the major Part 08 structures?

A register.

I need one specifically named state value to survive into later cycles. Which storage structure naturally fits?

A memory.

I need thousands of similar stored words and want to choose among them numerically. Which organization naturally fits?

A shift register.

I need the current stored word to become a repositioned version of itself every commanded cycle. Which structure naturally fits?

A counter.

I need the state itself to mean "how many?" or "how far?" Which sequential structure naturally fits?

A multiplexer.

I have several producers and one consumer, and control must determine which producer reaches that consumer. Which routing structure naturally fits?

A bus.

I need to transport a WIDTH-bit operand as one architectural object. Which Part 08 abstraction naturally describes that connection?

Tri-state architecture.

Several external devices may physically connect to the same line but must take turns actively driving it. Which architecture addresses this problem?

Persistence across time.

What does a register add that a purely combinational path does not provide?

The register commits a selected value as remembered machine state.

What architectural event separates a transient combinational result from persistent state?

Combinational logic proposes; storage commits.

What compact rule distinguishes combinational calculation from registered state?

Current state → next-state logic → committed next state.

What general pattern appears in registers, shift registers, counters, and other sequential datapaths?

The current stored value.

What provides the historical information needed when a sequential structure computes its next state from its previous state?

Because the register preserves information after the combinational conditions that produced it may have changed.

Why does storage introduce time into a datapath?

A temporal boundary.

What architectural boundary does a register establish between present-cycle computation and future-cycle state?

A shift register transforms the positions of its stored bits, whereas an ordinary hold operation preserves their positions.

What distinguishes shifting from merely retaining a register value?

Parallel load replaces the stored word with external data; shift derives a repositioned next word from current stored state.

What is the key distinction between LOAD and SHIFT in ShiftRegister.v?

reset → load → shift → hold

What is the complete priority order of ShiftRegister.v?

Reset wins and DataOut becomes zero.

What happens if reset, load, and shift are all asserted at the same active edge in ShiftRegister.v?

Load wins and ParallelIn becomes the new DataOut.

What happens if load and shift are asserted together while reset is low?

DataOut retains its previous state.

What happens when reset, load, and shift are all low?

Because the RTL uses mutually exclusive if/else paths rather than independent state updates.

Why can ShiftRegister.v perform only one of reset, load, shift, or hold for a particular clock edge?

A synchronous reset.

What kind of reset is implemented when reset is tested inside always @(posedge clk)?

The next positive clock edge.

If synchronous reset becomes asserted between clock edges, when does DataOut actually clear?

{WIDTH{1'b0}}

What parameter-safe expression creates the all-zero reset word in ShiftRegister.v?

It generates exactly WIDTH zero bits regardless of the selected parameter value.

Why is {WIDTH{1'b0}} better than hard-coding an 8-bit reset constant in a parameterized shift register?

Logical right shift.

What type of shift does DataOut >> 1 perform in the current unsigned ShiftRegister design?

A zero enters the MSB and the previous LSB is discarded.

What happens at the two ends of DataOut during a one-position logical right shift?

The current DataOut value.

In DataOut <= DataOut >> 1, which version of DataOut supplies the bits used to calculate the next state?

After WIDTH uninterrupted right shifts, the stored word becomes all zeros.

What eventually happens to any WIDTH-bit word repeatedly shifted logically right with zeros entering the MSB?

It stores numerical state whose encoding itself has mathematical meaning.

What makes a counter a specialized state machine?

The number represents an ordered position or amount of progress.

What architectural meaning distinguishes counter state from arbitrary FSM state encoding?

An incrementer computes X + 1; a counter stores successive numerical states across time.

What is the essential distinction between an incrementer and a counter?

Storage plus numerical next-state logic.

What must be added to an incrementing combinational operation to create persistent counter behavior?

Elapsed cycles, processed bits, addresses, sequence positions, event totals, or protocol progress.

What are examples of meanings a counter's numeric state can represent?

FSM = qualitative phase; counter = quantitative progression.

What compact distinction separates the natural roles of a general FSM and a counter?

The FSM can remain in RUN while the counter changes on every iteration.

How can a machine make sequential progress without changing its qualitative FSM state?

Terminal-count comparison.

What mechanism converts a counter's numerical state into a condition such as "the required amount of progress has been reached"?

Because the numerical encoding already expresses an ordered relationship among the states.

Why does a counter not necessarily require a separate descriptive name for every state?

A multiplexer selects which candidate source reaches a destination.

I see several existing values but only one may continue toward a shared consumer. What routing operation is required?

The select signal.

Which multiplexer information belongs conceptually to the control side?

The candidate data inputs and selected output.

Which multiplexer information belongs conceptually to the datapath side?

Control determines the route while data travels through that route.

What controller/datapath relationship is embodied by a multiplexer?

Selection chooses a value; transformation changes a value.

What is the difference between a MUX operation and an arithmetic operation?

Many producers → selection network → one consumer.

What topology summarizes multiplexing?

Fan-out is one source feeding many consumers; multiplexing is many candidate sources feeding one selected destination.

What is the difference between fan-out and multiplexing?

case (Operation)

What top-level RTL construct acts conceptually as the arithmetic engine's large result-selection network?

Operation.

Which persistent control state determines which arithmetic result is routed toward DisplayValue?

DisplayValue.

Which shared bus receives the selected and formatted arithmetic-engine result?

The unselected results can still exist on their separate internal nets.

What happens to other arithmetic results when one result is selected for DisplayValue?

Observability changed, not necessarily whether the internal computations exist.

If Operation changes which result appears on the LEDs, what may have changed even if the candidate arithmetic results themselves did not?

Result selection chooses which operation's information is used; formatting determines how that information fits the shared output representation.

What is the distinction between result selection and result formatting?

Because different functional units can naturally produce differently shaped information, such as comparator flags versus arithmetic words.

Why may a shared result bus require formatting logic in addition to a MUX?

A bus.

What abstraction allows a designer to treat many related physical wires as one architectural information path?

Width, meaning, direction, ownership, and timing.

What properties should you identify to understand a bus architecturally?

The number of bits transported together.

What does bus width specify?

Its semantic role.

Two buses are both 8 bits wide. What determines whether one is an operand bus and the other is an address bus?

Data bus = what value; address bus = where; control bundle = what action; status bundle = what condition.

What compact distinction separates the major bus roles?

Address tells WHERE; data tells WHAT; control tells WHAT ACTION.

What three-part bus model is especially useful for memory interfaces?

One source → many consumers.

What interconnection pattern describes operand fan-out?

A and B can fan out to multiple arithmetic units.

How can several arithmetic modules receive the same top-level operands simultaneously?

Separate result buses carry unit outputs before selection chooses one for DisplayValue.

How do buses and multiplexing cooperate in the arithmetic engine's output architecture?

No; a bus is an architectural abstraction and does not necessarily imply a literal shared electrical conductor.

Does every use of the term "bus" mean multiple devices physically drive one common wire set?

Because the interface must define not merely what bits exist but also when those bits are valid or sampled.

Why is timing part of a bus contract?

Z.

Which tri-state condition means "I am not driving this line"?

0 means actively driving low; Z means relinquishing the line.

Why must logic 0 and high impedance never be treated as equivalent?

The intended owner drives 0 or 1 while non-owners remain in Z.

What is the fundamental safe-ownership rule for a tri-state shared line?

Bus contention.

What occurs when multiple active drivers attempt to force conflicting values onto the same shared physical line?

Mutually exclusive drive ownership.

What control guarantee prevents two devices from actively fighting over a shared line?

Release → transfer ownership → drive.

What conceptual sequence describes safe bus turnaround between two potential drivers?

All potential drivers are in Z.

What condition exists during a no-drive interval on a tri-state line?

Contention means too many conflicting active drivers; no-driver means no source currently drives the line.

What is the distinction between contention and a released line?

MUX = logical source selection; tri-state = controlled electrical ownership of a shared physical line.

What is the architectural distinction between multiplexing and tri-state sharing?

Modern FPGA internal routing normally uses programmable interconnect and multiplexing.

How are internal signal routes generally realized in an FPGA rather than through arbitrary internal tri-state buses?

External I/O pins.

Where is true tri-state behavior most directly relevant in FPGA designs?

Because an external pin may need to drive a shared conductor during one interval and electrically release it during another.

Why can FPGA I/O require true tri-state behavior?

A memory.

What structure scales retained state into a regular collection of addressable words?

A register is typically named by role; a memory word is selected by address.

What is the core organizational distinction between register storage and memory storage?

Word width = bits per location; depth = number of locations.

What is the distinction between memory width and memory depth?

2^A locations.

How many distinct locations can A address bits naturally identify?

8 bits.

How many address bits are needed to select among 256 memory locations?

10 bits.

How many address bits are needed to select among 1024 memory locations?

Depth × word width.

How is total memory capacity in bits calculated?

Address selection.

What mechanism converts a numerical address into access to a particular member of a memory array?

Address = where; data = what.

What compact distinction separates a memory address from memory contents?

The selected location is the source of data.

What role does an addressed memory location play during a read?

The selected location is the destination of new data.

What role does an addressed memory location play during a write?

Memory → consumer.

What is the fundamental data direction of a memory read?

Producer → memory.

What is the fundamental data direction of a memory write?

A write modifies retained memory state; a read conceptually observes retained state.

What is the key state-change distinction between memory reads and writes?

Write enable.

Which control signal conceptually authorizes replacement of the selected stored word?

Address determines where; write enable determines whether that selected state is changed.

Why are address selection and write authorization separate?

SRAM.

Which memory architecture discussed in Part 08 retains stored state while powered without DRAM-style periodic refresh?