IE2104 CMOS Electrical Behavior & Logic Interfacing Flashcards

Vocabulary practice flashcards covering steady-state and dynamic electrical behavior, noise margins, fanout calculations, logic gate subfamilies, and low-voltage standards.

Static Behavior (Circuit Analysis)

The electrical behavior of a digital circuit when input and output signals are constant and NOT changing (steady-state).

Dynamic Behavior (Circuit Analysis)

The electrical behavior of a digital circuit when input and output signals are actively changing or transitioning between logic states.

Voltage Transfer Characteristic (VTC)

The curve mapping the relationship between the input voltage ($V_{\text{IN}}$) and the resulting output voltage ($V_{\text{OUT}}$) of a logic gate, such as a CMOS inverter.

Undefined Region (VTC)

The input voltage range (e.g., $2.2\,\text{V} \sim 2.6\,\text{V}$ on a typical $5\,\text{V}$ CMOS inverter curve) where the output transitions sharply and the output logic state cannot be guaranteed.

V_OHmin ($V_{\text{OHmin}}$)

The minimum output voltage guaranteed by a logic gate in the HIGH output state.

V_OLmax ($V_{\text{OLmax}}$)

The maximum output voltage guaranteed by a logic gate in the LOW output state.

V_IHmin ($V_{\text{IHmin}}$)

The minimum input voltage recognized by a logic gate as a valid HIGH state.

V_ILmax ($V_{\text{ILmax}}$)

The maximum input voltage recognized by a logic gate as a valid LOW state.

Power-Supply Rails

The supply voltage ($V_{\text{CC}}$ or $V_{\text{DD}}$) and ground (GND) lines that determine and scale typical CMOS logic switching thresholds.

DC Noise Margin

A quantitative measure of a circuit's immunity to noise, defining how much noise voltage can corrupt a worst-case output signal before an input fails to recognize it properly.

Low-State Noise Margin ($NM_{\text{L}}$)

The maximum noise voltage allowable on a LOW logic level without exceeding $V_{\text{ILmax}}$, calculated as $NM_{\text{L}} = V_{\text{ILmax}} - V_{\text{OLmax}}$.

High-State Noise Margin ($NM_{\text{H}}$)

The maximum noise voltage allowable on a HIGH logic level without dropping below $V_{\text{IHmin}}$, calculated as $NM_{\text{H}} = V_{\text{OHmin}} - V_{\text{IHmin}}$.

I_IH ($I_{\text{IH}}$)

The maximum current that flows into an input terminal when a HIGH-level voltage is applied.

I_IL ($I_{\text{IL}}$)

The maximum current that flows out of an input terminal when a LOW-level voltage is applied.

Sourcing Current

Current flow direction where current flows out of the logic gate output terminal from the internal power supply ($V_{\text{CC}}$) through the load to ground, occurring when the PMOS transistor is ON and the NMOS is OFF.

Sinking Current

Current flow direction where current flows from an external supply through the load into the logic gate output terminal to ground, occurring when the NMOS transistor is ON and the PMOS is OFF.

I_OHmax ($I_{\text{OHmax}}$)

The maximum sourcing current an output can supply in the HIGH state while maintaining an output voltage of at least $V_{\text{OHmin}}$.

I_OLmax ($I_{\text{OLmax}}$)

The maximum sinking current an output can absorb in the LOW state while maintaining an output voltage no greater than $V_{\text{OLmax}}$.

Gate Fanout

The maximum number of driven inputs a single logic gate output can drive without exceeding worst-case loading current ratings or violating logic voltage specifications, given by $\text{Fanout} = \min(N_{\text{H}}, N_{\text{L}})$.

Tie-Off Design Rules

Circuit design guidelines requiring that unused CMOS gate inputs must never float; unused NAND inputs are tied HIGH ($V_{\text{DD}}$) through a $1\,\text{k}\Omega$ resistor, and unused NOR inputs are tied LOW (GND) through a $1\,\text{k}\Omega$ resistor.

Transition Time

The time required for the output of a logic circuit to switch from one logical voltage state to another.

Propagation Delay ($t_p$)

The time delay between the midpoint ($50\%$) of an input signal transition and the corresponding midpoint ($50\%$) of the resulting output signal transition, establishing the fundamental speed limit of a digital circuit.

t_pHL ($t_{\text{pHL}}$)

Propagation delay measured from the $50\%$ input transition point to the $50\%$ output transition point when the output is switching from HIGH to LOW.

t_pLH ($t_{\text{pLH}}$)

Propagation delay measured from the $50\%$ input transition point to the $50\%$ output transition point when the output is switching from LOW to HIGH.

Open-Drain Gate

A specialized logic gate that omits the internal PMOS pull-up transistor, having only an NMOS pull-down transistor, requiring an external pull-up resistor to produce a valid HIGH logic state.

74FAMnn Mnemonic System

Alphanumeric designator format for standard 74-series ICs where FAM identifies the technology subfamily generation (e.g. HC, AHC) and nn specifies the numeric logic function (e.g. 00 for NAND).

54-Series Logic

Military and aerospace grade sub-series of digital logic components specified for wider operating temperature ranges ($-55\,^{\circ}\text{C}$ to $125\,^{\circ}\text{C}$) and tighter power supply tolerances than commercial 74-series components.

74HC Family

High-speed CMOS logic subfamily designed for pure CMOS systems, operating across a wide power supply range from $2\,\text{V}$ to $6\,\text{V}$.

74HCT Family

High-speed CMOS logic subfamily designed with lower input threshold voltage boundaries ($V_{\text{IHmin}} = 2.0\,\text{V}$, $V_{\text{ILmax}} = 0.8\,\text{V}$) to enable direct interfacing with legacy TTL logic outputs at $V_{\text{CC}} = 5\,\text{V}$.

74AHC Family

Advanced High-speed CMOS logic subfamily featuring sub-micron transistor scaling to achieve 2 to 3 times faster propagation speeds ($t_{\text{PD}} \approx 3.7\,\text{ns}$ for '00) than standard 74HC logic.

Symmetric Output Drive

Output driver property where a logic gate exhibits equal sourcing and sinking current drive strengths ($|I_{\text{SOURCE}}| = |I_{\text{SINK}}|$).

Power-Dissipation Capacitance ($C_{\text{PD}}$)

An internal device capacitance parameter used to calculate dynamic power dissipation in CMOS logic circuits using the formula $P = C_{\text{PD}} \cdot V_{\text{CC}}^2 \cdot f$.

74LVC Family

Low-Voltage CMOS logic subfamily designed for mixed-voltage systems, featuring over-voltage tolerant inputs up to $5.5\,\text{V}$ while operating from lower supply voltages (e.g., $3.3\,\text{V}$).

74ALVC Family

Advanced Low-Voltage CMOS logic subfamily optimized for ultra-high-speed processing at $2.5\,\text{V}$ and $3.3\,\text{V}$, achieving sub-2 nanosecond ($< 2\,\text{ns}$) propagation delays.

3.3V LVTTL

Low-voltage digital logic interfacing standard whose input and output voltage thresholds ($V_{\text{OHmin}} = 2.4\,\text{V}$, $V_{\text{IHmin}} = 2.0\,\text{V}$, $V_{\text{OLmax}} = 0.4\,\text{V}$, $V_{\text{ILmax}} = 0.8\,\text{V}$) match classic 5V TTL levels.

Transistor-Transistor Logic (TTL)

A bipolar junction transistor (BJT) logic family requiring a standard $5.0\,\text{V}$ DC power supply and offering inherent immunity to electrostatic discharge (ESD).

Schottky Clamping

The integration of a Schottky diode between the base and collector of a BJT to divert excess base current and prevent deep transistor saturation, reducing turn-OFF propagation delay.

74LS Family

Low-power Schottky TTL subfamily utilizing Schottky-clamped BJTs to balance modest propagation delay ($9\,\text{ns}$) with low power dissipation ($2\,\text{mW}$ per gate).