Pipelining — HIGH PRIORITY

Pipelining

CPU technique that overlaps the execution of multiple instructions by dividing instruction processing into stages.

Pipeline

A sequence of stages through which instructions move during execution.

Pipeline stage

One step of instruction processing performed while other instructions are in different stages.

Pipeline throughput

Number of instructions completed during a given amount of time.

Pipeline hazard

A condition that prevents the next instruction from executing during its expected clock cycle.

Data hazard

Pipeline hazard caused when one instruction depends on the result of an earlier instruction.

Control hazard

Pipeline hazard caused by branches or other changes in instruction flow.

Structural hazard

Pipeline hazard caused when multiple instructions need the same hardware resource at the same time.

Dependency

Relationship where one instruction requires data produced or used by another instruction.

Stall

Deliberate pause in the pipeline until a hazard is resolved.

Pipeline bubble

Empty pipeline slot created when execution must temporarily stall.

Forwarding

Sends a result directly from one pipeline stage to another without waiting for it to be written back to a register.

Branch prediction

CPU attempts to predict the result of a branch so pipeline execution can continue without waiting.

Pipeline speedup

Performance improvement gained by overlapping instruction execution rather than completing one instruction before starting anothe