WEEKS 11-14

Finite State Machine (FSM)

A computational model used to design sequential logic, represented by a set of states, transition functions, and output functions.

Mealy Machine

A type of FSM where the output depends on the current state and current input.

Moore Machine

A type of FSM where the output depends only on the current state.

Read-Only Memory (ROM)

Nonvolatile memory that retains its contents when power is removed, generally used for permanent data storage.

Programmable Logic Array (PLA)

A programmable device that can implement any function in sum-of-products form using an AND plane and an OR plane.

Electrically Erasable Programmable ROM (EEPROM)

A type of nonvolatile memory that allows for data to be erased and reprogrammed using electrical charge.

Flash Memory

A type of nonvolatile memory that can be electrically erased and reprogrammed, typically used in storage devices.

Truth Table

A mathematical table used to determine the functional output of combinational or sequential logic based on all possible input combinations.

Input Function

A function that defines how the output of a logic circuit depends on the input values.

Output Function

In FSM, the function that determines the outputs based on the current state and inputs.

Design for Testability (DFT)

A design approach aimed at making testing easier by improving controllability and observability of a chip's internal nodes.

Fault Models

Models that describe how faults can affect the behavior of a circuit, commonly including stuck-at faults.

Observability

The ease of observing the state of a node in a circuit by monitoring the external output pins.

Controllability

The ease of forcing a node in a circuit to a specific state (0 or 1) through the input pins.

Functional Verification

The process of ensuring that the design implementation correctly fulfills its specifications.

Testing

The process of applying test stimuli to circuit inputs and analyzing output responses for correctness.

Silicon Debug

The phase of testing where initial chips returned from fabrication are tested for logic bugs and electrical failures.

Built-In Self-Test (BIST)

A design feature that allows a chip to test itself using an internal test pattern generator and output response analyzer.

Test Pattern Generation

The process of generating sequences of test vectors needed to prove that a node is fault-free.

Stuck-At Fault

A fault model assumption where a node in a circuit is assumed to be stuck at logic 0 or logic 1.

Boundary Scan

A testing method that allows for the testing of solder joints and internal circuit connections through additional pins.

Logic Verification

Ensures that the chip's logic functions correctly, typically done at the HDL (Hardware Description Language) level.

Equivalence Checking

A formal verification method that checks if two different representations of a circuit are functionally equivalent.

Model Checking

A formal verification technique that systematically checks a model against specifications to find logical errors.

Test Vector

A specific input applied to a circuit to determine its behavior during testing.

Scan Design

A design technique that incorporates additional multiplexer circuitry to facilitate testing of sequential circuits.

Silicon Functional Testing

The process of verifying the functionality of manufactured chips to ensure they meet design specifications.

Memory arrays

Collections of memory cells that store data.

Random Access Memory (RAM)

Volatile memory used for temporary storage.

Static RAM (SRAM)

A type of RAM that retains data bits in its memory as long as power is being supplied.

Dynamic RAM (DRAM)

A type of RAM that needs to refresh its data periodically.

Content Addressable Memory (CAM)

Memory where data can be accessed based on content rather than address.

Read Only Memory (ROM)

Non-volatile memory used for permanent data storage.

Shift Registers

Memory elements that store data and shift the data in or out.

Binary tree decoder

A device that decodes input signals to produce a combination of outputs.

Sense Amplifier

Amplifier used to detect small levels of voltage in memory chips.

Soft Error Rate (SER)

The frequency with which soft errors occur, typically related to environmental factors.

Alpha particles

Helium nuclei emitted during radioactive decay that can cause soft errors in memory.

Precharge

Setting a line to a known voltage prior to reading or writing.

Multiplexer

Circuit that selects one of several input signals and forwards the selected input into a single line.

Dual-Ported SRAM

Memory setup allowing two simultaneous read/write operations.

1T DRAM Cell

A dynamic RAM cell design that uses a single transistor for data storage.

12T SRAM Cell

An SRAM design that provides better stability but occupies more area compared to 6T.

Cell Address

The unique identifier for accessing a specific memory cell in an array.

Write Recovery

Time taken to change a memory state after writing.