Hardware

A 470 Ω resistor is connected across 24 V. What current flows?

Start with V=IR. Rearrange: I=V/R. I=24/470=0.0511 A, which is 51.06 mA. Answer: about 51.06 mA. Bigger resistance would give less current for the same voltage.

A 470 Ω resistor has 5 V across it. How much power becomes heat?

Use P=VI and I=V/R, so P=V²/R. P=5²/470=0.053 W. Answer: 0.053 W. The resistor power rating must safely exceed the expected dissipation.

R1=2200 Ω goes from 3.3 V to Vout and R2=10000 Ω goes from Vout to ground. With no load, what is Vout?

The same current flows through R1 and R2. Vout is the fraction across R2: Vout=Vin×R2/(R1+R2)=3.3×10000/(2200+10000)=2.705 V. Answer: about 2.705 V.

An RC filter uses R=22000 Ω and C=10 nF. What is its cutoff frequency?

Use fc=1/(2πRC). Substituting gives fc=1/(2π×22000×1e-08)≈723.4 Hz. At this frequency a first-order filter is about -3 dB, or 0.707 of passband amplitude.

A 0.1 µF capacitor sees a 1000 Hz sine wave. What is its reactance magnitude?

Use Xc=1/(2πfC). Xc=1/(2π×1000×1e-07)≈1591.55 Ω. Higher frequency would make Xc smaller because the capacitor passes faster-changing current more easily.

A 100 mH inductor sees a 1000 Hz sine wave. What is its reactance magnitude?

Use Xl=2πfL. Xl=2π×1000×0.1≈628.32 Ω. Higher frequency makes an inductor oppose current changes more strongly.

An RC circuit has R=2200 Ω and C=1 µF. What is its time constant?

Use τ=RC. τ=2200×1e-06=0.002200 s = 2.200 ms. After one τ a first-order charging response has completed about 63 percent of its total change.

An LED drops about 2.0 V. You want 5 mA from a 3.3 V supply. What series resistor is needed?

The resistor must drop the leftover voltage: 3.3-2.0=1.3 V. Use R=V/I=1.3/0.005≈260 Ω. Choose a nearby standard value, usually rounding up slightly to limit current.

A BJT is in active region with β=150 and base current 50 µA. Estimate collector current.

Use the simple active-region relation Ic≈βIb. Ic=150×50 µA=7.50 mA. This is an estimate and should not be trusted for a saturated switch.

A fully-on MOSFET has RDS(on)=20 mΩ and carries 0.5 A. Estimate voltage drop and conduction loss.

Model the on MOSFET as a small resistor. Vdrop=IR=0.5×0.02=0.010 V. Power=I²R=0.5²×0.02=0.005 W. That electrical loss becomes heat.

A MOSFET needs 80 nC of gate charge and the driver can source about 0.5 A. Roughly how long does moving that charge take?

Current is charge per second: I=Q/t, so t=Q/I. t=8e-08/0.5=160.0 ns. This is only a rough switching-time estimate, but it shows why a stronger gate driver can switch a large MOSFET faster.

An ideal inverting amplifier has Rin=10000 Ω, Rf=4700 Ω and Vin=0.5 V. What output does it request before supply limits?

Gain=-Rf/Rin=-4700/10000=-0.470. Then Vout=gain×Vin=-0.470×0.5=-0.235 V. The minus sign means inversion, not that every output must always be below ground.

An ideal non-inverting amplifier has Rg=4700 Ω, Rf=10000 Ω and Vin=1 V. What output does it request before supply limits?

Gain=1+Rf/Rg=1+10000/4700=3.128. Vout=3.128×1=3.128 V. In real hardware confirm the supply rails, output swing and common-mode range can support this.

An op-amp has gain-bandwidth product about 20 MHz and closed-loop gain 10. Estimate bandwidth.

For a simple one-pole compensated op-amp, gain×bandwidth is roughly constant. Bandwidth≈GBW/gain=20 MHz/10=2000.0 kHz. Check the real datasheet for an exact design.

A linear regulator drops 9 V to 5 V while supplying 0.05 A. How much power does the regulator turn into heat?

The regulator drops 4.0 V while the same load current flows. Ploss=(Vin-Vout)I=(9-5)×0.05=0.200 W. That is why large voltage drops at high current need thermal care.

An ideal buck converter changes 48 V to 5 V. Roughly what duty cycle is required?

For an ideal buck, Vout≈D×Vin. So D=Vout/Vin=5/48=0.104, or about 10.4 percent. Real losses and control details shift it slightly.

What decimal value does binary 01011001 represent?

Use place values 128,64,32,16,8,4,2,1. Add the values where the bit is 1. The total is 89. Answer: 89.

Two unsigned 4-bit values are 11 and 11. Their sum is stored back into only 4 bits. What value is stored?

The true sum is 22. A 4-bit register holds values modulo 2^4=16. Stored value=22 mod 16=6. Extra carry bits are lost unless you make the result wider.

Two unsigned 8-bit values are 17 and 13. Their sum is stored back into only 8 bits. What value is stored?

The true sum is 30. A 8-bit register holds values modulo 2^8=256. Stored value=30 mod 256=30. Extra carry bits are lost unless you make the result wider.

A 8-bit timer uses a 16 MHz clock with prescaler 1. What is one tick and the overflow time from zero?

Timer clock becomes 16000000.0 Hz. One tick=prescaler/source clock=1/1.6e+07=0.062 µs. There are 256 counts, so overflow=256×0.062 µs=0.016 ms.

A PWM is HIGH for 37 counter counts out of 100 total counts. What is its duty cycle?

Duty is the fraction of each period that the output is HIGH. Duty=37/100×100=37.00 percent. Higher duty means more average voltage/power for a slow load.

An ideal 16-bit ADC uses a 3.3 V reference and measures 1.542 V. Roughly what code should it produce?

Maximum code is 65535. Code≈Vin/Vref×max=1.542/3.3×65535≈30620. One ideal LSB is about 0.050 mV.

A UART runs at 9,600 baud. About how long does a 10-bit frame take?

At this UART setting, one bit lasts 1/9600 s=104.167 µs. A 10-bit frame takes 10×that=1041.667 µs.

An I2C bus has pull-up 1000 Ω and total capacitance about 50 pF. What is the RC time constant?

Use τ=RC. τ=1000×5e-11=50.0 ns. The actual logic rise takes several fractions/multiples of τ depending on thresholds. Larger R or C makes the bus rise more slowly.

A proportional controller has Kp=10, setpoint=1 and measurement=15. What P command does it produce?

First compute error e=setpoint-measurement=1-15=-14.00. Then u=Kp×e=10×-14.00=-140.00. The sign tells the correction direction.

A proportional controller has Kp=0.5, setpoint=20 and measurement=8. What P command does it produce?

First compute error e=setpoint-measurement=20-8=12.00. Then u=Kp×e=0.5×12.00=6.00. The sign tells the correction direction.

A first-order system has time constant τ=0.05 s. After 4τ following a step, roughly what percentage of its final change is complete?

Use fraction=1-exp(-t/τ). At t=4τ, fraction=1-exp(-4)=0.9817, or 98.2 percent. Remember about 63 percent at 1τ and over 99 percent by 5τ.

A first-order system has time constant τ=0.01 s. After 5τ following a step, roughly what percentage of its final change is complete?

Use fraction=1-exp(-t/τ). At t=5τ, fraction=1-exp(-5)=0.9933, or 99.3 percent. Remember about 63 percent at 1τ and over 99 percent by 5τ.

A first-order system has time constant τ=0.05 s. After 2τ following a step, roughly what percentage of its final change is complete?

Use fraction=1-exp(-t/τ). At t=2τ, fraction=1-exp(-2)=0.8647, or 86.5 percent. Remember about 63 percent at 1τ and over 99 percent by 5τ.

A first-order system has time constant τ=2 s. After 1τ following a step, roughly what percentage of its final change is complete?

Use fraction=1-exp(-t/τ). At t=1τ, fraction=1-exp(-1)=0.6321, or 63.2 percent. Remember about 63 percent at 1τ and over 99 percent by 5τ.

A first-order system has time constant τ=0.1 s. After 3τ following a step, roughly what percentage of its final change is complete?

Use fraction=1-exp(-t/τ). At t=3τ, fraction=1-exp(-3)=0.9502, or 95.0 percent. Remember about 63 percent at 1τ and over 99 percent by 5τ.

A register path has clock period 4 ns, clock-to-Q 0.4 ns, logic+routing 7 ns and setup time 0.8 ns. Ignoring skew, what is setup slack?

Total required path time=0.4+7+0.8=8.20 ns. Available time=4 ns. Slack=4-8.20=-4.20 ns. Negative slack means data arrives too late, so the path fails setup timing.

A register path has clock period 5 ns, clock-to-Q 0.2 ns, logic+routing 2.5 ns and setup time 0.2 ns. Ignoring skew, what is setup slack?

Total required path time=0.2+2.5+0.2=2.90 ns. Available time=5 ns. Slack=5-2.90=2.10 ns. Positive slack means this simplified setup check passes.

An FPGA block runs at 250 MHz and accepts one new item every 1 clock cycle(s). What is peak throughput?

There are 250 million cycles each second. One item every 1 cycles gives 250.000 million items/s. This is throughput; latency can still be many cycles.

An analogue sensor reading jumps whenever a nearby digital output switches. What physical paths can couple the noise? What would you check before replacing components?

Think of shared impedance and fields: shared supply/ground voltage drops, capacitive coupling from fast dv/dt, inductive coupling from fast di/dt, and ADC reference disturbance. Probe the supply, reference and ground near the sensor.

A MOSFET is very hot even though average load current looks reasonable. What losses besides I²R should you think about? What mistake should you avoid?

Check switching loss from slow edges, gate-drive weakness, high switching frequency, diode/reverse-recovery effects, shoot-through and poor thermal path. Measure gate and drain waveforms, not only DC current.

An op-amp output is stuck at a supply rail. What are the first three checks? Explain the first measurement you would make.

Check whether the calculated output is inside the supply/output swing, whether feedback is truly negative and connected, and whether both input voltages are inside the allowed common-mode range.

An I2C bus works on the bench but fails after adding a long cable. What simple electrical parameter probably increased? Which principle is most important here?

Bus capacitance. The pull-up resistor must charge more capacitance, so SDA/SCL rise more slowly. Inspect rise time, cable topology and pull-up strength within device sink-current limits.

UART prints random characters even though wiring looks correct. What settings should you compare first? What would you check before replacing components?

Compare baud rate, data bits, parity and stop bits. Then verify clock accuracy, voltage levels, TX-to-RX crossing and common reference ground.

A multi-bit status bus crosses directly between unrelated FPGA clocks and occasionally shows impossible values. Why? What mistake should you avoid?

Different bits can be captured on different source transitions and individual synchronisers do not preserve word coherence. Use a handshake, stable-data protocol or asynchronous FIFO instead.

Timing fails by -0.8 ns on one FPGA path. What does the negative number mean? Explain the first measurement you would make.

The data path needs 0.8 ns more time than the constraint allows. Find whether delay is logic or routing dominated, then pipeline, simplify, improve placement or lower frequency if the architecture allows.

A button press is counted three times by firmware. What is the most likely physical cause? Which principle is most important here?

Mechanical contact bounce. One physical press creates several rapid electrical transitions. Use hardware filtering/Schmitt input or software debouncing that requires a stable level for a chosen time.

An ADC reading changes when you touch the probe to its input. What does that tell you? What would you check before replacing components?

The node is likely high impedance or sensitive to capacitance/noise. The probe itself is loading or stabilising it. Check source impedance, ADC acquisition time, grounding and whether a buffer is needed.

A relay transistor dies when the relay is switched off, not on. Why can turn-off be the dangerous moment? What mistake should you avoid?

The coil is an inductor and tries to keep current flowing. Interrupting it creates a large voltage spike. A correctly placed flyback path clamps that energy.

A control loop is smooth in simulation but oscillates on the real machine. Name four missing real-world effects to check. Explain the first measurement you would make.

Check delay/sample time, sensor filtering/noise, actuator saturation, friction/backlash, flexible resonances and parameter mismatch. Real plants contain dynamics and limits the simple model may omit.

A PID motor controller reaches 100 percent output and stays there while error remains large. What should you conclude? Which principle is most important here?

The actuator is saturated and cannot provide the requested correction. Check whether the target is reachable, the mechanism is jammed, power is sufficient, and anti-windup prevents the integrator from growing without benefit.

An FPGA counter works at 50 MHz but not 250 MHz. Why is the Boolean logic still correct but hardware wrong? What would you check before replacing components?

Correct function does not guarantee timing. At 250 MHz the period is only 4 ns, so combinational plus routing delay may exceed the time between registers. Check static timing and pipeline the critical path.

Two clocked SystemVerilog registers behave strangely because blocking assignments were used. Why can that happen? What mistake should you avoid?

Blocking assignments update immediately in procedural order during simulation, so a later statement can see a new value that real flip-flops would not see until after the edge. Use nonblocking assignments for clocked state.

A board works until a motor starts, then the MCU resets. What should you investigate first? Explain the first measurement you would make.

Treat this as a power/noise problem first. Check the supply rail on an oscilloscope during motor startup, motor current, ground return paths, decoupling, flyback/snubbers and whether the regulator enters current limit. The motor can create both a supply dip and switching interference.

A 3.3 V MCU output measures 3.3 V with no load but only 1.2 V after connecting a circuit. What does that suggest? Which principle is most important here?

The load is drawing too much current or pulling against the pin. Check output-current limits, shorts, wrong pin direction and whether another device drives the same line. A logic output is not an ideal voltage source.

At a PCB node, 20 mA enters. Two branches carry 1 mA and 3 mA away. What current must leave through the third branch, and why?

Charge cannot continuously pile up at the node. KCL says current entering equals current leaving. So I3=20-1-3=16 mA. The important idea is conservation of charge, not a memorised sign rule.

A relay coil is switched by a transistor. The transistor repeatedly fails when the relay turns off. The DC coil current is within rating. What electrical event are you missing, and what simple component would you add?

The coil is an inductor, so its current cannot stop instantly. When the transistor opens, the coil raises its voltage as high as necessary to try to keep current flowing, creating a large flyback spike. A flyback diode across the coil provides a safe current path while stored magnetic energy decays.

A half-bridge becomes extremely hot even at modest load. Oscilloscope traces show the high-side MOSFET has not fully turned off before the low-side turns on. What failure mechanism is occurring and how is it normally prevented?

Both MOSFETs briefly conduct at the same time, creating shoot-through directly from supply to ground. The current can be huge because the path resistance is very small. Gate timing is designed with dead time, and gate-drive strength/layout are chosen so one device is safely off before the other turns on.

A 1 mV bridge sensor must be amplified by 100×, but both sensor wires sit near 2.5 V and pick up the same 100 mV interference. What amplifier property is especially important?

You need strong differential gain for the 1 mV difference while rejecting voltage common to both wires. An instrumentation or differential amplifier with high CMRR is appropriate. High input impedance also avoids loading the bridge. The key idea is that useful information is the difference, while shared interference is common-mode.

A linear regulator converts 12 V to 3.3 V at 0.5 A. Estimate heat dissipation and idealised efficiency. Would you expect thermal problems?

The regulator drops 8.7 V while carrying 0.5 A, so heat≈(12−3.3)×0.5=4.35 W. Idealised efficiency is roughly Vout/Vin≈27.5%. That is substantial heat and likely needs thermal attention.

A 1 MHz square wave looks rounded on a 2 MHz oscilloscope even though 1 MHz is below the scope bandwidth. Why?

A square wave is not only its 1 MHz fundamental. Sharp edges require higher odd harmonics. A 2 MHz scope removes most of those harmonics, so the displayed waveform becomes rounded. Edge-rate measurement needs bandwidth well above the repetition frequency.

A one-clock pulse generated in a 100 MHz domain must be detected in an unrelated 20 MHz domain. Why can a simple two-flop synchronizer miss the event?

The pulse lasts only 10 ns, while destination edges are 50 ns apart. It can occur entirely between two destination edges, so no flip-flop ever samples it HIGH. Use pulse stretching, a toggle synchronizer, request/acknowledge handshake, or an asynchronous FIFO depending on the data.

A DMA engine fills a RAM buffer, but the CPU keeps reading old values from its cache. What architectural issue is this?

The CPU’s cached copy is stale because DMA changed memory without using the CPU’s normal cache path. The system needs hardware cache coherence or explicit software cache maintenance/invalidation according to the architecture.

A 16-bit timer runs from 48 MHz with prescaler 256. Find the timer tick and overflow time.

Timer frequency becomes 187.5 kHz. One tick is prescaler/clock=5.333 µs. There are 2^16=65536 counts, so overflow time≈349.5 ms. Hardware timers count independently of CPU instruction timing.

A strain gauge changes resistance only slightly under load. Why is a Wheatstone bridge plus instrumentation amplifier a sensible measurement chain?

The bridge converts a tiny resistance change into a small differential voltage and can provide temperature/common-effect cancellation. The instrumentation amplifier then amplifies that small difference while presenting high input impedance and rejecting much of the common-mode voltage before the ADC.

A CAN bus has a 120 Ω termination at every node instead of only at the two physical ends. What electrical problem can that create?

All those resistors appear as a much lower total load, forcing the transceivers to drive excessive current and reducing signal amplitude. A normal linear CAN bus is terminated with its characteristic impedance at the two ends, not at every node.

A stable first-order plant has time constant τ=0.1 s. After 5τ following a step, roughly what fraction of the final change has occurred?

First-order fraction completed is 1−e^(−t/τ). At 5τ, this is about 99.33%. One τ gives about 63%; five τ gives over 99%. The time constant tells you the natural speed of the response.

You write a synthesizable for loop with a fixed bound of 16 to add 16 independent terms. Does the FPGA automatically perform one addition per clock for 16 clocks?

No. A static RTL loop is usually elaborated/unrolled into hardware structure. It may create many adders/combinational logic in parallel unless you explicitly design a sequential architecture with registers, a counter and one reused adder. HDL describes hardware, not software instruction execution.

A design’s 200-cycle calculation has a pipeline that accepts one input every clock and runs at 250 MHz. What are its latency and steady-state throughput?

Latency is 200 cycles × 4 ns/cycle = 800 ns. But once the pipeline is full, it can still accept and potentially produce one result every cycle, so throughput is 250 million items/s. Latency and throughput are different quantities.

A digital input works with a short jumper but fails through a 2 m cable. What changes electrically when the wire becomes long?

The cable adds capacitance, inductance, resistance and antenna coupling. With fast edges it can behave as a transmission line, creating slower edges, ringing and noise pickup. Consider differential signalling, proper termination, slower edge rate or a more robust physical interface.

An N-channel MOSFET has gate=5 V, source=4.2 V and drain=12 V. Someone says “the gate is 5 V, so it must be on.” What is the actual control voltage and what would you conclude?

The relevant quantity is gate-to-source voltage: VGS=5−4.2=0.8 V. That is probably too small to turn an ordinary enhancement N-MOSFET on strongly. Gate voltage must always be considered relative to source, which is why high-side N-MOSFETs need special gate-drive circuitry.

An ideal inverting op-amp has Rin=2200 Ω, Rf=4700 Ω and Vin=0.2 V. Find the requested output. Then explain why the inverting input sits near 0 V if the non-inverting input is grounded.

Closed-loop gain is −Rf/Rin=−4700/2200=-2.136, so Vout≈-0.427 V. Negative feedback drives the input difference toward nearly zero, so V−≈V+=0 V. This is a virtual ground: near 0 V electrically, but not physically connected to ground and ideally drawing almost no input current.

A second-order low-pass has a large resonant peak and rings after a step. Which parameter is likely too high, and what does that tell you physically?

Its Q is likely high, meaning damping is low. Energy near the natural frequency persists instead of dying quickly, so the frequency response peaks and the time response oscillates. Frequency-domain peaking and time-domain ringing are two views of the same dynamics.

A converter inductor is rated 10 µH, but above 4 A the current waveform suddenly becomes much steeper and the MOSFET overheats. What likely happened?

The inductor likely entered magnetic saturation. In saturation its inductance falls sharply. Since di/dt≈V/L, lower L makes current rise faster, increasing ripple and peak current. Inductor saturation current must therefore exceed the expected peak current with margin.

A push-pull 3.3 V output and a push-pull 5 V output are accidentally tied to the same net. One drives HIGH while the other drives LOW. What happens electrically?

The outputs fight each other. One transistor network tries to source current while the other sinks it, creating a low-resistance path between supplies/ground. The signal becomes invalid and the drivers can overheat. Shared buses need controlled tri-state, open-drain signalling, or another defined interface.

A 32-bit little-endian processor stores value 0x12345678 starting at address 0x1000. Which byte appears at the lowest address?

Little-endian stores the least-significant byte first. 0x12345678 has bytes 12 34 56 78 from most to least significant, so address 0x1000 contains 0x78, then 0x56, 0x34 and 0x12.

A variable is updated inside an interrupt and read in main(). You add volatile. What problem does that solve, and what problem does it NOT solve?

volatile tells the compiler that the value can change unexpectedly, so it must actually perform the memory access instead of assuming a cached value. It does not make a multi-byte read atomic, prevent races, or provide locking. Those require separate synchronisation or critical sections.

An I²C bus works with one sensor but fails after adding a long cable and four devices. SDA rises very slowly on the scope. What changed and what parameter would you adjust?

The extra devices and cable increased bus capacitance. SDA/SCL rise through the pull-up resistor, so rise time is approximately an RC effect. Lower the pull-up resistance within the devices’ allowed sink-current limits, reduce capacitance/length, slow the bus, or use an appropriate buffer.

A motor PID works well at first, but after the motor hits its maximum command for several seconds it overshoots badly when it finally catches up. What happened?

The actuator saturated, but the integrator kept accumulating error. This integral windup stores a large command that remains even after the system approaches the target. Anti-windup stops or back-calculates the integrator while the actuator is saturated.

An asynchronous event pulse is occasionally lost when sent into another clock domain. You mark the path false_path and timing reports become green. Is the hardware now safe?

No. false_path only tells static timing analysis not to enforce a synchronous timing relationship. It does not create a synchronizer or prevent metastability/event loss. Implement a correct CDC structure first, then constrain it appropriately.

A serial bus fails only after several minutes, then recovers after reset. What categories of problem should you consider?

Consider buffer overflow, state-machine deadlock, missed timeout, accumulated errors, thermal drift, power noise and a peripheral stuck mid-transaction. Capture logs and bus traces around failure rather than resetting immediately, because the failure state contains evidence.

A 5 V logic input can tolerate only 5.5 V, but a cable may experience short 20 V spikes. What sort of protection element could clamp the spike, and what else must be true for it to survive?

A TVS diode or suitable clamp can conduct strongly when voltage rises beyond a chosen level, diverting surge current away from the input. The clamp must have an appropriate standoff/clamp voltage, and the source/path must limit surge current so the protection device’s pulse-energy rating is not exceeded.

You measure a very small shunt resistance with two multimeter leads and get a value dominated by the leads. How does a four-wire Kelvin measurement fix this?

Two wires force the test current through the unknown resistance. Two separate high-impedance sense wires measure voltage directly at the component terminals and carry almost no current, so their own resistance creates negligible voltage drop. Then R=V/I reflects the component rather than the leads.

A register path has Tclk=5 ns, clock-to-Q=1 ns, combinational delay=7 ns and setup=1 ns. Ignoring skew, calculate setup slack and decide if the path passes.

Data needs 9 ns before the next edge. Slack=5−9=-4 ns. It fails because negative slack means the data arrives too late. Setup timing is fundamentally a race between data-path delay and the next sampling edge.

A GPIO pin drives a relay coil directly and the MCU resets when the relay switches. Identify at least two electrical design mistakes.

A GPIO usually cannot safely supply relay-coil current, so use a transistor/MOSFET driver. The coil is inductive, so add a flyback path. Also provide local decoupling and sensible return-current layout because the switching transient can disturb the MCU supply/ground.

A DC motor draws 8 A at startup but only 2 A once spinning. Explain this without treating the motor as a mysterious load.

At zero speed, back EMF is essentially zero, so current is limited mainly by the winding resistance: I≈V/R. As the motor spins, it acts like a generator and produces back EMF opposing the supply. The effective voltage across the resistance falls, so current drops.

Two CAN nodes start transmitting IDs 0x120 and 0x080 at the same time. Which message wins arbitration and why is the losing frame not corrupted?

0x080 wins because lower numerical identifiers have higher priority. CAN uses dominant/recessive bit arbitration. A node that sends recessive but reads dominant realises it lost and stops transmitting, while the winner continues its original frame unchanged.

A position loop becomes unstable after you add a heavy low-pass filter to make the sensor reading smoother. How can “less noise” reduce stability?

The filter also adds phase lag/delay. The controller is now acting on an older version of the real motion. Around the loop crossover frequency, enough extra phase lag can turn corrective negative feedback toward positive feedback and reduce phase margin.

Two clocked registers are updated in one always_ff block. Why should you normally use nonblocking <= rather than blocking =?

Real flip-flops sample their inputs from the old state at the same clock edge and update outputs together. Nonblocking assignments model that behaviour. Blocking assignments update immediately in procedural order and can make one register accidentally see another register’s new value in simulation.

A 12-bit binary counter must cross from clock A to unrelated clock B. Why is putting a two-flop synchronizer on every bit not enough?

Several binary bits can change on the same count transition, but each synchronizer resolves independently. Clock B can therefore see a mixture of old and new bits that never existed. Use an asynchronous FIFO, handshake, or for pointer-like values convert to Gray code so only one bit changes between adjacent counts.

A 10 µF capacitor is connected to a 1000 Hz sine-wave source. Find |Xc|. If frequency doubles, what happens to |Xc|?

|Xc|=1/(2πfC)≈15.92 Ω. Frequency is in the denominator, so doubling frequency halves the reactance. A capacitor therefore opposes slow changes more than fast changes.

A 3.3 V MCU must switch a 200 mA load using an NPN BJT. Using forced β=10 and VBE≈0.7 V, estimate the base resistor.

Required base current is Ib=Ic/10=20 mA. The resistor sees about 2.6 V, so R≈V/I=2.6/0.02≈130 Ω. Forced beta is deliberately lower than datasheet small-signal beta so the transistor is driven firmly into saturation.

An ideal non-inverting amplifier has Rg=10000 Ω, Rf=10000 Ω and Vin=0.5 V. Find its requested output before supply limits.

Gain=1+Rf/Rg=1+10000/10000=2. So Vout≈2×0.5=1 V. Negative feedback forces the divided output at the inverting input to match the input voltage.

You are measuring a slowly changing sensor and add an RC low-pass with R=10000 Ω and C=1000 nF. Find fc. What happens to fast noise well above fc?

fc=1/(2πRC)≈15.92 Hz. A first-order low-pass increasingly attenuates components above fc, with an asymptotic slope near −20 dB/decade. The trade-off is that real fast sensor changes are also slowed.

A buck converter works electrically but radiates noise into a nearby sensor. Which PCB regions should you inspect first and why?

Inspect the high-dI/dt current loops and the switch node. Rapid current change through loop inductance creates voltage spikes, and rapid switch-node voltage creates electric-field coupling. Keep these loops short/tight, the switch-node copper compact, use good decoupling, and separate sensitive analogue return paths.

A 100 mV sensor signal runs beside a motor cable. Both sensor wires pick up nearly the same 200 mV interference. Why can a differential receiver still recover the sensor signal?

A differential receiver responds mainly to V+−V−. Noise added nearly equally to both wires is common-mode and largely cancels in the subtraction. Twisted pairs help both wires experience similar interference, improving rejection.

An asynchronous input changes extremely close to a flip-flop clock edge. The output takes unusually long to settle. What physical effect is this, and why can you not design it away completely?

This is metastability caused by setup/hold violation. The flip-flop’s internal analogue nodes temporarily sit between stable logic states. You cannot make the probability exactly zero, but synchronizer stages give extra time to resolve so the probability of propagation becomes extremely small.

A firmware ring buffer is used for UART RX. The write pointer catches the read pointer because the consumer is too slow. What design decision must be explicit?

You must define full-buffer behaviour: drop newest data, overwrite oldest, assert an error, or apply flow control. A ring buffer only absorbs temporary rate mismatch; it cannot fix a producer that permanently outruns the consumer.

A UART uses 8N1 at 1,000,000 baud. About how long does one 10-bit frame take and why can two devices fail if their baud clocks differ too much?

Frame time≈10/1000000=10 µs. UART has no shared clock wire; the receiver samples based on its own clock after detecting the start bit. Small clock error is tolerated, but too much accumulated timing error moves sample points toward neighbouring bits.

A testbench changes an input at exactly the same simulation time as the DUT’s rising clock edge, and the result changes when code is rearranged. What kind of problem is this?

It is a simulation race. Testbench stimulus and DUT sampling compete in the same time slot. Drive stimulus away from the sampling edge or use SystemVerilog clocking blocks/event regions so the intended ordering is explicit.

A circuit works at room temperature but fails when hot. Which component parameters should you remember are temperature-dependent?

Semiconductor threshold/forward voltages, leakage, MOSFET RDS(on), BJT gain, oscillator frequency, resistor values, sensor offsets and timing can all shift. Thermal failures often expose a design that had very little margin.

An ideal LC network uses L=100 mH and C=1 µF. Estimate its resonant frequency and explain what is happening physically at resonance.

f0=1/(2π√(LC))≈503.3 Hz. At resonance, the magnitudes of inductive and capacitive reactance are equal. Energy repeatedly moves between the capacitor’s electric field and the inductor’s magnetic field, which is why the circuit has a natural frequency.

Using the simple 0.7 V silicon-diode model, 1 forward-biased diodes are in series from a 12 V source. Roughly what voltage remains after them, and why is 0.7 V only a model?

Total estimated diode drop is 1×0.7=0.7 V, so about 11.3 V remains. The real forward voltage depends on current, temperature and diode construction; 0.7 V is a convenient first estimate, not a fixed physical constant.

A common-emitter amplifier’s collector output falls when the base voltage rises. Explain the chain of events from input to output.

A higher base-emitter drive increases transistor collector current. More collector current causes a larger voltage drop across the collector resistor. Since Vcollector=VCC−Icollector·RC, the collector voltage falls. So the stage inverts: input up produces output down.

An FSM output should depend only on the stored state, not directly on current input signals. Is this Moore or Mealy style, and what practical behaviour follows?

It is Moore style. Because outputs come from registered state, they usually change only after a state update on a clock edge and are less directly sensitive to input glitches. A Mealy output can react within the same cycle but requires more care with combinational timing.