CPU Structure & Instruction Flashcards

CPU

Key Components of CPU Organization

Control Unit, ALU, MU

CPU Organization

The structure and functioning of the CPU

Control Unit

Directs the operation of the CPU and manages the data.

ALU

It executes all arithmetic and logical operations.

Memory Unit

Stores and receives the execution data of the CPU

Type of Processors

Single Core Processors, Dual-Core Processors, Quad-Core Processors

Single Core Processors

Single-core CPUs are the earliest type of computer processors, first used in the 1970s. They have only one core, so they can process only one task at a time and are not suitable for multitasking.

Dual-Core Processors:

Dual-core CPUs use a single integrated circuit with two cores. Each core has its own cache and controller, allowing them to work together as one unit. Because of this, dual-core CPUs are faster and more efficient than single-core processors.

Quad-Core Processors

Quad-core CPUs have four independent cores on a single chip. These cores can read and execute multiple instructions at the same time, which improves overall performance. Quad-core CPUs increase program speed without needing to increase the clock speed.

Pipelining

A series of stages, where some work is done at each stage in parallel. The work is not finished until it has passed through all stages.

RISC

Reduced Instruction Set Computer

What does the organization of the CPU impacts on?

CPU organisation affects how the processor handles data processing, decision-making, memory communication, and instruction execution. A well-organised CPU coordinates these components efficiently, improving system speed, accuracy, and overall performance.

Instruction cycle

Fetch

Decode

Execute

Memory Access

Registry Write-Back

What are the challenges in Modern CPU Instruction Execution

Pipeline Hazards, Branch Prediction Errors, Instruction Cache Misses, Instruction, Resource Contention

When does pipeline hazards occurs?

1. occur when one instruction depends on the result of a previous instruction.

2. There are control flow changes (e.g., branches).

3. Hardware resources are not available for all pipeline stages.

Branch Prediction Errors

Results in wasted cycles and lower execution efficiency.

Instruction Cache Misses

High cache miss rates can significantly degrade CPU performance.

Instruction

Instruction-Level Parallelism (ILP) has practical limits, where adding more hardware no longer results in significant performance improvements.

Resource Contention

Efficient resource scheduling and hardware design help minimize this issue.

Pipeline

It is a technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed