Chapter 5 - Instruction Pipelining

What are the three stages of the laundry example?

Wash dirty clothes, dry wet clothes, fold and put clothes into drawers.

How long does sequential laundry take for 4 loads?

6 hours.

What are the three stages of the laundry example?

Wash dirty clothes, dry wet clothes, fold and put clothes into drawers.

How long does sequential laundry take for 4 loads?

6 hours.

What is the speedup factor when using pipelined laundry for 4 loads?

How much time does it take to wash, dry, and fold one load in both sequential and pipelined laundry?

90 minutes.

What is the role of the pipeline in laundry execution?

Overlap the execution stages allowing tasks to enter and leave the pipeline at different rates.

How long does pipelined laundry take for 4 loads?

3 hours.

What is instruction pipelining?

It is a parallel execution of smaller steps in the fetch-decode-execute cycle to increase throughput.

What are the five stages of the RISC-V processor pipeline?

Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory access (MEM), Write Back (WB).

What is a data hazard?

A situation where execution is incorrect due to dependencies between instructions.

What is a RAW hazard?

Read After Write hazard, where an instruction needs to read an operand before it has been written by a previous instruction.

What are some solutions to resolve data hazards?

Stalling the pipeline, data hazard detection, forwarding, and code scheduling.

What causes control hazards?

The flow of control through branch instructions that affects the next instruction fetched.

How does pipelining improve task execution?

By allowing different stages to execute in parallel, leading to one completion per time unit instead of one for every k time units.

What is the maximum speedup achievable with a 5-segment pipeline with a task taking 200ns on a non-pipelined system?

What happens during a bubble or pipeline stall?

A delay in the execution of an instruction to resolve a hazard.

What is the timing of structures within a pipelined system based on maximum stage delays?

Clock cycle is determined as the maximum time delay in any stage.