CPU Struction & Instruction

CPU Organisation

The structure and functioning of the CPU

Single Core Processors

• One processing unit

• Executes one task at a time

Dual Core Processors

• Contain a single Integrated Circuit with two cores

• Each core has its cache and controller

Quad Core Processor

• Contain two dual-core processors present within a single integrated circuit (IC) or chip

• Increases the overall speed for programs

CPU Instruction Cycle

The sequence of steps performed by the CPU to execute a single instruction

Fetch Stage

CPU retrieves the next instruction from main memory (RAM)

Decode

The CPU interprets the instruction

Execute

The CPU carries out the instruction

Memory Access

Reads data from or writes data to main memory (RAM)

Registry Write-Back

The result is stored in a register or memory

Control Unit

Directs the operation of the CPU and manages The data

Arithmetic Logic Unit (ALU)

Executes all arithmetric and logical operations

Memory Unit

Stores and retrieves the execution data of the CPU

Pipeline Hazards

Problems that occur in a pipelined CPU when the next instruction cannot execute in its scheduled clock cycle, causing delays

Branch Prediction Errors

Results in wasted cycles and lower execution efficiency

Data Hazards

Occur when an instruction uses the result of the previous instruction

Control Hazards

The location of an instruction depends on previous instruction

Structural Hazards

Two or more instructions need the same hardware at the same time

RISC (Reduced Instruction Set Computer)

CPU architecture design that uses a small, simple set of instructions so each instruction can execute very fast, often in one clock cycle.

Instruction Cache Misses

High cache miss rates can significantly degrade CPU performance