Parallel Hardware and Software Concepts

SIMD

Single Instruction, Multiple Data processing model.

MIMD

Multiple Instruction, Multiple Data processing model.

Cache Coherence

Ensures consistency of shared data in caches.

Shared Memory

Memory accessible by multiple processes.

Distributed Memory

Memory not shared, accessed via message passing.

Von Neumann Architecture

Classic computer architecture with CPU and memory.

Control Unit

Part of CPU that directs operations.

Arithmetic and Logic Unit (ALU)

Executes arithmetic and logical operations.

Registers

Fast storage within CPU for program state.

Program Counter

Register holding the next instruction address.

Interconnect

Transfers data between CPU and memory.

Bus

Parallel wires for data transfer in computers.

Fetch

Reading instructions from memory to CPU.

Write to Memory

Storing data from CPU back to memory.

Von Neumann Bottleneck

Limitations due to separation of CPU and memory.

Operating System (OS)

Software managing hardware and software resources.

Process

Instance of a program being executed.

Executable Code

Machine language instructions for CPU execution.

Call Stack

Tracks active function calls in memory.

Heap

Dynamic memory allocation area for processes.

Security Information

Access control for process resources.

Process State

Current status of a process (ready, waiting).

Multitasking

Simultaneous execution of multiple processes.

Caching

Temporary storage for faster data access.

Locality Principle

Programs access memory in predictable patterns.

Spatial Locality

Accessing nearby memory locations.

Temporal Locality

Reaccessing the same memory location quickly.

Virtual Memory

Extends main memory using secondary storage.

Instruction-Level Parallelism (ILP)

Executing multiple instructions simultaneously.

Pipelining

Dividing instruction execution into stages.

Multiple Issue

Executing multiple instructions at once.

Static Multiple Issue

Instruction scheduling done at compile time.

Dynamic Multiple Issue

Instruction scheduling done at run time.

Superscalar

Processor supporting dynamic multiple issue.

Speculation

Guessing instruction execution to improve performance.

Hardware Multithreading

Executing multiple threads to utilize CPU resources.

Thread-Level Parallelism (TLP)

Parallelism through simultaneous thread execution.

Fine-Grained Multithreading

Switching threads after each instruction.

Coarse-Grained Multithreading

Switching threads only when stalled.

Simultaneous Multithreading (SMT)

Multiple threads using multiple functional units.