Levine et al. paper

What is erasure qubit?

Qubit architecture where most physical errors are detectable erasures instead of unknown Pauli errors

If error occurs, system knows which qubit failed

Dramatically improved error-correction thresholds!

Threshold ~1% for Pauli errors, up to ~50% for erasure errors

Erasures reveal location, so decoder has far less uncertainty

Dual-rail qubit

Encodes logical information across two physical modes: |0L> = |10>, |1L> = |01>

One excitation distributed across two transmons

Logical states correspond to which transmon holds excitation

Loss of excitation produces |00>, lying outside computational subspace → detection

Why do standard superconducting qubits not naturally prodyuce erasure errors?

Typical errors include phase errors, bit flips, leakage

Errors don’t reveal location

For erasure correction, need mechanism that converts dominant noise processes (T1 decay) into detectable eventsH

How is dual-rail qubit implemented experimentally?

Two resonantly coupled transmons:

Identical frequency tuning

Strong exchange coupling

Encoding restricted to single-excitation subspace

Hamiltonian is H = \omega(a_1^\dagger a_1 + a_2^\dagger a_2) + J(a_1^\dagger a_2 + a_2^\dagger a_1)

Logical qubit in {|10>, |01>}

How does T1 decay become erasure error?

Loss of excitation: |10> → |00> or |01> → |00>

|00> is outside logical subspace, so measurement can detect it

Energy relaxation is detectable erasure, not unknown error

Why is dephasing suppressed in encoding?

Qubit occupies symmetric single-excitation manifold, where many noise sources affect both rails similarly

Common-mode noise cancels

Essentially, |10> ←→ |01> is protected against slow fluctuations

How to detect erasure without collapsing logical qubit?

Measure whether system occupies single-excitation subspace

Distinguish between logical subspace: |10> or |01>

Doesn’t distinguish between logical states, so qubit coherence is preserved

Why important for QEC?

Error correction requires mid-circuit measurements

If erasure detection caused large dephasing, benefit vanishes

Experiment shows <0.1% dephasing per check → extremely small!

Coherence times achieved?

Logical subspace coherence reaches millisecond scale

Much longer than typical coherence of single transmons (~100 microseconds)

Improvement from noise suppression, encoding, erasure-conversion of T1 processes

Measured erasure probability per gate?

p_erasure roughly equal to 2.2 × 10^-3, with residual errors being ~40x smaller

Most errors are detectable! In near-erasure-dominant regime

Limitations of gate fidelity?

Excitation loss (T1) limits fidelity, where loss crucially produces erasures rather than logical errors

Residual errors come from imperfect calibration, leakage to higher transmon levels, and control noise

Can architecture scale to large processors?

Yes, though with tradeoffs

Pros are high erasure threshold, hardware-level error conversion

Challenges are requirement of two transmons/qubit, more couplers, more calibration complexity

Why are erasures powerful for decoding?

Decoder knows where error occurred → reducing decoding complexity dramatically

Surface-code thresholds increase from ~1% to ~50% for pure erasures

Codes that benefit from erasure qubits?

Surface codes, fusion-based QC, cluster state architectures

Main contribution of paper?

Hardware design converts dominant noise into erasures, where instead of fighting noise → architecture alters structure to make errors detectable

Tunable transmons?

Enable frequency matching, tunable coupling, and dynamic gate control

Maintaining symmetric subspace would be hard without tunability

Limitations?

Doubled hardware overhead, possible leakage to higher transmon levels, complexity of control

Need to demonstrate multi-qubit gates, integration into error-correcting codes in later work

Does erasure detection slow down computation?

Introduces extra measurements, but overhead is small

Erasure errors easier to correct, so overall error-correction overhead may decrease

If T1 is dominant noise source, why not improve T1 instead of building erasure qubits?

Eliminating noise completely is hard! Architecture instead accepts T1 loss, transforming it into detectable erasures → error correction operates much more efficiently

T1 vs. T2 errors

Tansmon T1 error is energy relaxation of a transmon qubit |1> → |0>

In the dual-rail encoding, this relaxation moves the system outside the logical subspace |10>, |01>, producing the detectable state ∣00⟩

Architecture converts dominant physical error channel, transmon T1 decay, into detectable erasure

T2 dephasing error (|0> + |1> → |0> + e^{i \phi} |1>), but T1 is roughly less than T2 → relaxation is dominant error

Scaling challenges remain, but architecture designed s.t. largest physical error channel becomes detectable

Do we know measurement doesn’t introduce backaction that becomes logical dephasing over time?

Doesn’t resolve logical basis (distinguishing only between {|10>, |01>} vs. |00>) → measurement operator acts as M = P_logical + P_00, where P_logical = |10><10|+|01><01|

Both logical states in same projector, so measurement commutes with logical Z operator → coherence preserved

Measure <0.1% dephasing/check, confirming repeated erasure checks introduce little logical decoherence

Correlated loss events?

Surface-code thresholds assume independent erasures

If two transmons share environment/coupler, correlated T1 events might occur

Erasure advantage is spatial independence of erasures: to mitigate correlations, can rely on physical separation of rails (each logical qubit uses two transmons, but engineered to have separate decay channels), and decoder robustness (surface-code decoders can tolerate correlated erasures if correlation length is small)

Hardware overhead?

Require two transmons instead of one: does this cancel gains from higher error thresholds?

Key tradeoff between physical qubit count and logical qubit overhead → surface-code threshold is up to ~1% for Pauli errors, while erasures are up to ~50% for erasures

Prevent undetected leakage errors

Higher excited states: population leaks into them → system could stay inside single-excitation manifold of dual-rail encoding, but corrupt logical state

Suppressing mechanisms:

1. Operating in single-excitation subspace: Logical states have just one excitation, which reduces multi-photon leakage pathways

2. Gate design: pulses engineered to minimize transitions into |2> states

3. Spectral separation: transmon anharmonicity helps suppress unwanted transitions

Leakage is possible non-erasure error channel: need further work to detect leakage, convert leakage into erasures, actively reset leaked states

Is this really new?

Indeed, dual-rail encoding looks like two-mode bosonic code restricted to single-excitation manifold

But! Uses standard transmon hardware, requires no large photon-number states, naturally converts T1 errors into erasures