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Fetch Stage
The Control Unit breaks down the instruction to understand what action is required.
Execute Stage
The CPU carries out the operation, such as performing a calculation.
Write-Back Stage
The result of the execution is saved back into a register or memory.
ALU (Arithmetic Logic Unit)
The part of the CPU that handles math (addition/subtraction) and logic (AND/OR).
Control Unit (CU)
The "manager" of the CPU that directs the flow of data and instructions.
Program Counter (PC)
A register that holds the address of the next instruction to be fetched.
Instruction Register (IR)
A storage area that holds the current instruction being decoded or executed.
Accumulator
A register used to store intermediate arithmetic and logic resul
Pipelining
A technique where multiple instructions are processed overlappingly to save time.
Pipeline Hazard
A situation that prevents the next instruction from executing in the designated clock cycle.
Data Hazard
Occurs when an instruction depends on the result of a previous instruction that isn't finished yet.
Structural Hazard
Occurs when two instructions try to use the same hardware resource at the same time.
Control Hazard
Caused by delay in determining the next instruction (usually due to branches/jumps).
RISC (Reduced Instruction Set Computer)
A CPU design that uses a small set of simple, fast-executing instructions.
CISC (Complex Instruction Set Computer)
A CPU design where a single instruction can perform multiple low-level operations.
One Cycle Execution
A RISC characteristic where most instructions are completed in a single clock cycle.
Fixed-Length Instructions
A RISC feature where every instruction is the same size, making decoding easier.
CPU Clock
A signal that synchronizes all CPU components; measured in Gigahertz (GHz).
System Bus
The "pathway" used to move data between the CPU, memory, and I/O devices.