Flashcards for Data Representation and Basic Computer Organization (Lecture Notes)

Key terms and definitions covering floating-point representation, binary codes (Gray, BCD, ASCII/EBCDIC), error-detection, memory and I/O, and the basic computer's RTL, bus, ALU, and instruction cycle.

Mantissa

The signed fixed-point part of a floating-point number that contains the significant digits.

Exponent

The part of a floating-point number that designates the position of the radix point; in decimal, it indicates how many places to shift the decimal; in floating-point, the base–radix is raised to this power.

Fraction (mantissa in floating-point)

The mantissa portion (fixed-point) that, together with the exponent, represents the value of a floating-point number.

Normalization (floating-point)

A floating-point number is normalized when the most significant digit of the mantissa is nonzero; zero cannot be normalized.

Radix

The base of a numeral system (e.g., 10 for decimal, 2 for binary). In floating-point, the radix and the exponent position are assumed by the hardware.

Floating-point representation

A number is represented by a mantissa (significant) and an exponent that indicate the scale for the radix point.

Normalized number

A floating-point number where the leftmost digit of the mantissa is nonzero, giving maximum precision.

Gray code

A binary code in which successive values differ by only one bit, reducing ambiguity during transitions.

Reflected Binary Code (Gray code)

AGray code where the sequence is formed by reflecting the previous values; used to minimize bit changes between successive numbers.

Gray code counter

A counter that cycles through Gray code sequence to avoid multi-bit changes during transitions.

Excess-3 Gray

A Gray code sequence shifted by 3 (adding 3 to the code) to improve decimal digit transitions and reduce transitions per digit.

Binary-Coded Decimal (BCD)

A binary representation of decimal digits using 4 bits per digit; digits may be encoded in different variants like 8421, 2421, or Excess-3.

8421 code

A weighted BCD code where each digit’s 4 bits have weights 8, 4, 2, and 1.

2421 code

A weighted BCD code with bit weights 2, 4, 2, 1 used to form decimal digits; has self-complementing properties for some operations.

Excess-3 code

A decimal code in which each decimal digit is represented by its BCD value plus 3 (unweighted).

Self-complementing code

A code in which the 9’s complement of a decimal digit can be obtained by flipping bits (0s to 1s and 1s to 0s).

9's complement

The 9’s complement of a decimal number; in certain codes, it is easy to obtain by bitwise complement.

10's complement

The 10’s complement of a decimal number; used for subtraction in binary arithmetic.

ASCII

The American Standard Code for Information Interchange; a 7-bit character code (128 characters) commonly used for transmission; often with an 8th parity bit.

ASCII 7-bit

The standard 7-bit ASCII encoding that represents 128 characters (graphic, control, and formatting).

EBCDIC

Extended Binary Ccoded Interchange Code; an 8-bit IBM character code with the same characters as ASCII but different bit assignments.

Parity bit

An extra bit added to a binary word to enforce an odd or even number of 1s for error detection.

P(odd)

The parity bit that makes the total number of 1s odd in a given word.

P(even)

The parity bit that makes the total number of 1s even in a given word.

Parity generator

A circuit that computes the required parity bit for a given message.

Parity checker

A circuit that checks whether the received word has the correct parity according to the chosen scheme.

1's complement

A bitwise NOT operation yielding the bitwise negation of a binary number.

2's complement

A method of representing negative numbers by inverting bits and adding one to obtain the negation.

Full-adder

A circuit that adds two bits with a carry-in, producing a sum bit and a carry-out.

Binary adder

A cascade of full-adders used to add multi-bit binary numbers.

Adder-subtractor

A circuit that can perform addition or subtraction by controlling inputs; often uses XOR with a mode bit to flip B for subtraction.

Incrementer

A circuit that adds one to a binary number; can be implemented with half-adders or a counter.

Common bus

A shared set of wires (bus) connecting multiple registers; data is transferred via controlled selection from a subset of registers.

Multiplexer (MUX)

A device that selects one of several input data lines and forwards the chosen input to a single output line.

Three-state bus (tri-state) buffers

Buffers that can be enabled or placed in a high-impedance state to allow multiple devices to share a common bus without interference.

Register Transfer Language (RTL)

A symbolic notation used to describe the microoperation sequences and data transfers among registers.

Replacement operator

Notation like R2 <- R1 indicating the contents of R1 are transferred to R2 and the source remains unchanged.

Memory word (M)

A word stored in memory; the memory word located by the address in AR is denoted as M.

Memory read

Operation that reads a memory word into a register, e.g., DR <- M[AR].

Memory write

Operation that writes a register’s content to a memory location, e.g., M[AR] <- AC.

Memory address register (MAR)

Register that holds the memory address for the next memory operation.

Instruction register (IR)

Register that holds the current instruction being decoded and executed.

Program counter (PC)

Register that holds the address of the next instruction to be fetched.

Accumulator (AC)

Primary processing register used for arithmetic and logic operations.

Data register (DR)

Register that temporarily holds data read from memory before processing.

Temporary register (TR)

Register used to hold temporary data during processing.

Indirect addressing

Addressing mode where the operand’s address is found by first reading a pointer from memory.

Direct addressing

Addressing mode where the address part directly gives the memory address of the operand.

Effective address

The actual memory address used in a computation; for indirect addressing, it is the address found via pointer in memory.

Memory-reference instruction

An instruction that requires a memory operand (uses AR to reference M[AR]).

Register-reference instruction

An instruction that operates only on processor registers without memory reference.

Input-output instruction

An instruction that transfers information between I/O devices and the processor registers.

I bit (indirect addressing bit)

Bit in memory-reference instructions that selects indirect (I=1) vs direct (I=0) addressing.

Fetch–Decode–Execute cycle

The sequence of steps to fetch an instruction, decode it, perform address calculation, and execute the operation.

Indirect address (example concept)

An addressing step where the memory word at AR contains the address of the operand.

Opcode

The operation code bits in an instruction that specify which operation to perform.

Stored-program organization

Concept that instructions are stored in memory and executed sequentially by the processor.

Opcode formats (3-bit vs 16-bit codes)

Different organizations of operation codes: a 3-bit opcode for MRI and a 16-bit code for other instructions.

Instruction set completeness

Having a sufficient set of instructions (arithmetic, memory, I/O, control) to compute any computable function.

Clock cycle / timing signals

The clock-driven timing signals (T0, T1, etc.) that synchronize register transfers and microoperations.

Interrupt (IEN, FGI, FGO)

Mechanism to temporarily suspend the CPU to handle I/O or other events; includes interrupt enable (IEN) and flags (FGI, FGO).