Computer Architecture and Organization - Midterm 1

What is the minimum number of bits the number 0x1001 requires?

A. 4

B. 13

C. 16

D. 2

E. None of the above

C

Assembly language is just an easier way of writing machine code.

A. True

B. False

A

Convert 8_777 to Hexadecimal.

A. 0x1FF

B. 0x777

C. 0x511

D. 0x1F7

E. None of the above

A

Convert 2_1011010011010001 to Decimal.

A. 23144

B. 132321

C. 46289

D. 23145

E. None of the above

C

Convert 375 to Octal.

A. 177

B. 567

C. 159

D. 765

E. None of the above

B

The Programmer's Model refers to the aspects of the microprocessor that ___.

A. can be manipulated using machine code.

B. are unique to the hardware.

C. require access in a higher-level language.

D. control the internal model.

E. None of the above

?

The native (or natural) data size for a processor is known as ___.

A. a data size of 32 bits

B. the word size

C. the data register

D. byte size

E. None of the above

B

The number 0x8F represents ___.

A. 143

B. 8_217

C. -113

D. 113

E. None of the above

B

The number -25 is an example of a ___.

A. one's complement number

B. two complement number

C. sign-magnitude number

D. bit encoded number

E. None of the above

C

Add the following two 8-bit unsigned numbers: 0xFF + 0x03=___.

A. 0x02

B. -0x02

C. 0x102

D. 0xFF03

E. None of the above

A

The ARM-2 instruction set contains only 32-bit instructions to maximize speed.

A. True

B. False

B

Our assembler is an isomorphic compiler.

A. True

B. False

A

Perform the operation using 8 bits and 2's complement: -5 + 0x12 = ___.

A. 2_00001101

B. 2_00010111

C. 2_11101101

D. 2_10001101

E. None of the above

A

Perform the operation using 8 bits and 2's complement: 2_11111101 + 2_00001000 = ___.

A. 2_00000101

B. 2_100000101

C. 2_011111101

D. 2_11111101

E. None of the above

A

Perform the operation using 8 bits and 2's complement: 8_360 + 0x0A = ___.

A. 8_36A

B. 8_372

C. 0x36A

D. 0x373

E. None of the above

B

Perform the operation using 8 bits and 2's complement: 0xFF - 0xFA = ___.

A. 0xF9

B. 0x1F9

C. 0x05

D. -0x05

E. None of the above

C

All CPUs follow the ___ cycle.

A. Decode -> Fetch -> Execute

B. Execute -> Decode -> Fetch

C. Fetch -> Decode -> Execute

D. None of the above

C

Multiple Execute units in a CPU are indicative of ___ architecture.

A. simple sequential execution

B. pipelined execution

C. superscalar execution

D. multiprocessing execution

E. None of the above

C

Consider the data located in program memory below:

address [[contents]]

0x1000 0000 [[0xAE]]

0x1000 0001 [[0xBB]]

0x1000 0002 [[0xA0]]

0x1000 0003 [[0xC0]]

The number in little endian format is ___.

A. 0xC0A0BBAE

B. 0xA0C0AEBB

C. 0xAEBBA0C0

D. 0xBBAEC0A0

E. None of the above

A

Consider the following memory state:

0x1000 0000 [[ 0x0000 FFFF ]] [[ ]]

0x1000 0004 [[ 0x1000 000C ]] [[ ]]

0x1000 0008 [[ 0x1000 0010 ]] [[ ]]

0x1000 000C [[ 0x1000 0000 ]] [[ ]]

0x1000 0010 [[ 0xC0A0 BBAE ]] [[ ]]

address memory memory

r0 [[ 0x1000 0008 ]] [[ ]]

r1 [[ 0x1000 000C ]] [[ ]]

r2 [[ 0x0000 0004 ]] [[ ]]

cpu registers cpu registers

.

Consider the following code:

LDR r2, [r0, #8]!

.

What is the value of r0 after the code has been executed?

A. 0x10000008

B. 0x10000004

C. 0x1000000C

D. 0x10000010

E. None of the above

Most often used load/store instructions

Loads Stores Size and Type

LDR STR Word (32 bits)

LDRB STRB Byte (8 bits)

LDRH STRH Halfword (16 bits)

LDRSB Signed byte

LDRSH Signed halfword

LDM STM Multiple words

The first three types of instructions simply transfer a word, halfword, or byte to memory from a register, or from memory to a register. For halfword loads, the data is placed in the least significant halfword (bits [15:0]) of the register with zeros in the upper 16 bits. For halfword stores, the data is taken from the least significant halfword. For byte loads, the data is placed in the least significant byte (bits [7:0]) of the register with zeros in the upper 24 bit.s For byte stores, the data is taken from the least significant byte.

Signed halfword and signed byte load instructions deserve a little more explanation. The operation is: a byte or a halfword is read from memory, sign extended to 32 bits, then stored in a register. Here, the programmer is specifically branding the data as signed data.

Consider the instruction:

LDRH r11, [r0]; load a halfword into r11

Assuming the address in register r0 is 0x8000, before and after the instruction is executed, the data appears as follows:

Memory Address

r11 before load [[0xEE]] 0x8000

[[0x12345678]] [[0xFF]] 0x8001

r11 after load [[0x90]] 0x8002

[[0x0000FFEE]] [[0xA7]] 0x8003

Notice that 0xEE, the least significant byte at address 0x8000, is moved to the least significant byte in register r11, the second least significant byte, 0xFF, is moved to second least significant byte of register r11, etc.

Consider the instruction:

LDRSH r11, [r0]; load signed halfword into r11

It produces the following scenario, assuming register r0 contains the address 0x8000:

Memory Address

r11 before load [[0xEE]] 0x8000

[[0x12345678]] [[0x8C]] 0x8001

r11 after load [[0x90]] 0x8002

[[0xFFFF8CEE]] [[0xA7]] 0x8003

The two bytes from memory are moved into register r11, except the most significant bit of the value at address 0x8001, 0x8C, is set, meaning that in a two's complement representation, this is a negative number. Therefore, the sign bit should be extended, which produces the value 0xFFFF8CEE in register r11.

Addressing Options for Loads and Stores on the ARM7TDMI

Imm Scaled Reg

Offset Offset Examples

Word 12 bits supported LDR r0, [r8,r2,LSL #28]

Unsigned byte LDRB r4, [r8, #0xF1A]

Halfword 8 bits not supp. STRH r9, [r10, #0xF4]

Signed halfword LDRSB r9, [r2, r1]

Signed byte

STR r3, [r8]; store data to 0x8000

Memory Address

r8 before store [[0xBE]] 0x8000

[[0x00008000]] [[0xBA]] 0x8001

r8 after store [[0xED]] 0x8002

[[0x00008000]] [[0xFE]] 0x8003

STR r3, [r8], #4; store data to 0x8000

Memory Address

r8 before store [[0xBE]] 0x8000

[[0x00008000]] [[0xBA]] 0x8001

r8 after store [[0xED]] 0x8002

[[0x00008004]] [[0xFE]] 0x8003

load r5 with data from ea

LDR r5, [r3]

store data in r0 to ea<9>

STRB r0, [r9]

store data in r3 to ea

STR r3, [r0, 05, LSL #3]

load r1 from ea

LDR r1, [r0, #4]!

store byte to ea[r6-1>, r6=r6-1

STRB r7, [r6, #-1]!

load r3 from ea,r9=r9+4

LDR r3, [r9], #4

store word to ea, r5=r5+8

STR r2, [r5], #8

store r3 to ea (r0 unchanged)

STR r3, [r0, r5, LSL #3]

load r6 from ea>6)> (r0 updated)

LDR r6, [r0, r1, ROR #6]!

load r0 from ea

LDR r0, [r1, #-8]

load r0 from ea

LDR r0, [r1,-r2,LSL #2]

load signed halfword from ea

LDRSH r5, [r9]

load signed byte from ea

LDRSB r3, [r8, #3]

load signed byte from ea

LDRSB r4, [r10, #0xc1]

Pre-indexed addressing

the address of the data transfer is calculated by adding an offset to the value in the base register, Rn. The optional "!" specifies writing the effective address back into Rn at the end of the instruction. Without it, Rn contains its original value after the instruction executes:

STR r0, [r1, #12]

offset: 12

base register: r1

source register for STR: r0

Post-indexed addressing

the effective address of the data transfer is calculated from the unmodified value in the base register, Rn. The offset is then added to the value in Rn, and the sum is written back to Rn. This type of incrementing is useful in stepping through tables or lists, since the base address is automatically updated for you.

STR r0, [r1], #12

offset: 12

base register: r1

source register for STR: r0

store r7 to ea, then r0=r0+24

STR r7, [r0], #24

load halfword to r3 from ea, then r9=r9+2

LDRH r3, [r9], #2

store halfword from r2 to ea, then r5=r5+8

STRH r2, [r5], #8