Modules 9-10 - Pipelining and MIPS Architecture (Part 1)

The full form of MIPS is __________.

Microprocessor without Interlocked Pipeline Stages

MIPS architecture supports 32-bit version known as __________ and 64-bit version known as __________.

MIPS32, MIPS64

MIPS is developed based on general-purpose registers with a __________ architecture.

load-store

Data types and sizes in MIPS include 8/16/32/64-bit integers and __________ 754 floating-point numbers.

64-bit IEEE

MIPS provides at least __________ general purpose registers (GPR).

16

In MIPS, the value of register R0 is always __________.

0

Registers in MIPS architecture can be accessed with a __________ symbol.

$

The MIPS Program Counter (PC) contains the address of the __________ currently being retrieved from memory.

instruction

Integer multiplication results in a __________-sized result, placed in special registers hi and lo.

twice-register

Floating-point operations results are held in the __________ register.

floating-point status register (c1)

The integer data types in MIPS are 8-bit bytes, 16-bit half words, 32-bit words, and __________.

64-bit double words

Immediate addressing mode uses __________ bit displacement in MIPS architecture.

16-bit

The MIPS instruction set is categorized into __________ broad classes of instructions.

4

Load and store instructions categorized under MIPS instruction set include LB, LBU, SB, __________, LH, and SH.

LW

MIPS instruction format for loading from memory is L* rd, offset(rs) ; rd Mem[offset+(rs)].

When loading data to R0 register in MIPS, the result is __________.

discarded

Byte, half-word & word LOADs will place data on the __________ portion of the destination register.

least significant