4.7 Fundamentals of computer organisation and architecture

A bus

a set of parallel wires connecting two or more components of a computer

Addressable memory

the concept of storing data and instructions in a memory with discrete, unique addresses

Address bus

uni-directional, a bus that carries the memory location address of the register the data is being carried to and from

Control bus

bi-directional, used to send control signals that manage and orchestrate the operations that take place inside a computer system. This includes exchanging status signals between the components of the computer system, and transmitting clock signals required for the coordination of operations

Data bus

bi-directional, a bus for carrying data and instructions between the processor and memory

Harvard architecture

a computer architecture that stores data and instructions in separate memories to allow the next instruction to be read while data is currently being read or written

I/O controllers

an interface that allows the processor to communicate with input and output devices connected to the computer

Von Neuman architecture

a computer architecture where a single control unit manages program control via a linear sequence of fetch-decode and execute cycles. Data and instructions are held in the same memory.

Main memory

a data store for instructions for the processor that can be directly addressed by the processor

Processors

a complex chip of transistors capable of executing programs, computing data to outputs and supervising the operation of a computer system

What does the width of a bus refer to?

the number of parallel lines, which determines the number of bits that can be used to form an address

What does increasing the width of the address bus do?

adding a single wire doubles the number of addressable memory locations. 2 parallel wires=2^2(no. Of wires) so 4 addressable memory locations

How does the width affect affect the data bus?

Determines the number of bits that can be transferred in one operation. e.g. If a computer has a word size of 32 but with a 16-bit data bus, then the data bus has to fetch the word twice from the main memory.

Stored program concept

machine code instructions stored in main memory are fetched and executed serially by a processor that performs arithmetic and logical operations

Control unit

controls and coordinates the activities of within the CPU and controls the flow of data in and out of the CPU, takes instruction and decodes it into opcode and operands, manages execution and stores result

Clock

used to synchronise CPU operations, generates signals of alternating 0 and 1

General-purpose registers

very fast and small memory inside the CPU used to hold data before, during and after being processed by the CPU

Name of common GP register

accumulator

Dedicated registers: PC

program counter, holds the address of the next instruction

Dedicated registers: CIR

current instruction register, holds the currently being executed instruction

Dedicated registers: MAR

memory address register, holds the memory address of an instruction to be fetched or written to

Dedicated registers: MBR

memory buffer register, temporarily holds data moving between the processor and main memory

Dedicated registers: SR

status register, holds the bits to indicate the results of the execution of an instruction, such as overflow, negative, zero or carry over

Fetch

retrieves a program instruction from its memory

Decoding

determines what actions the instruction requires

Executing

carries out the decoded actions

Registers: fetch stage

PC keeps address of next instruction, contents of PC copied to MAR which is connected to the address bus. Address of next instruction is placed on the address bus. CU instructs a memory read operation to allow the contents of memory location to be transferred to processor. The instruction that is stored at that address is transferred using the data bus for main memory to processor and saved in MBR. PC incremented by 1. MBR copied to CIR. This ensures current instruction is kept safe so MBR can be used during the execute cycle in order to store additional data if needed.

Why is the PC incremented by 1?

in a sequential prog[ram the next instruction is typically in the next memory location however if next instruction involves branching to another place in the program the PC will adapt accordingly

Registers: Decode stage

CU decodes the instruction kept in CIR by splitting it into operand and opcode to determine what kind of instruction needs to be carried out, check if additional data is needed from memory and figure out where it is kept there.

Registers: Execute stage

Instruction is executed. The exact sequence of instructions depends on the type of instruction being executed. e.g. for an arithmetic instruction any required data is fetched from main memory and calculation performed by ALU result then stored in accumulator, general-purpose register or main memory.

Instruction set

a sequence of operations in machine code that can be recognised by a particular processor as the execution of a command

Opcode

the part of the instruction that specifies which operation the processor should perform and the addressing mode

Operand

the part of the instruction with a value, memory address or register that the instruction will act on during its execution

Characteristics of low-level languages

1 to 1 relationship with processor, non-portable, programs typically require less memory and execute faster

Immediate addressing

the operand us interpreted as a data value

Direct addressing

the operand is treated as a memory address

What is datum?

a singular piece of data

Assembly language: BRANCH

jumps to another part of the program

Assembly language: HALT

stops executing the program

Uses of low level languages

embedded systems, device drivers

What are device drivers?

they allow the CPU to communicate with peripherals

An interrupt

a signal sent to the processor to request immediate attention

What happens when the processor receives interrupt?

it suspends what it is doing and runs ISR

Interrupt service routine (IRS)

a mini program that has been designed to respond to an interrupt’s request. It can be built into an operating system or provided via device drivers

What happens after IRS is finished executing?

OS must return to instruction is was executing before it received the interrupt and continue from where it left off

Interrupts affect on the execution of the fetch-decode-execute cycle

processor receives interrupt, processor completes FDE of instruction it was running, current contents of the processor registers are saved to memory, origin if interrupt is identified so appropriate IRS is called, all other low-priority interrupts are put on hold to allow IRS to finish, program counter updated with address of the first instruction of the IRS, IRS completes execution, processor registers are reloaded with the values that were saved to memory, low-priority interrupts that were put on hold are re established

Factors affecting processor performance: multiple cores

multiples processors can carry out tasks in parallel, task can be split up to be run on different cores in parallel to speed up execution

Factors affecting processor performance: cache memory

depending on how close they are to the CPU they are classified as level 1,2,3,

Factors affecting processor performance: clock speed

increasing clock speed will execute more instructions per second

Factors affecting processor performance: word length

larger word length more data CPU can process, processor can access a larger amount of memory through direct addressing and have a larger instruction set

start 4.7.4 external hardware devices