Shift Registers

Shift Register

A sequential storage structure that can deliberately reposition the bits of its stored value across clock cycles.

Shift Register as a Data-Movement Structure

A register whose next-state behavior can change the positions of the bits already stored within it.

Storage + Controlled Repositioning

What two architectural capabilities are combined by a shift register?

The shift register calculates a repositioned version of its current stored word and commits that version as its next state.

Why is shifting considered a state transformation rather than merely movement through wires?

The current stored value.

From what value is the next shifted state derived?

Parallel Load

An operation that captures an entire multi-bit input word into the register during one clock event.

ParallelIn

The WIDTH-bit input bus containing the complete word that can be loaded into DataOut.

DataOut

The WIDTH-bit register that both stores the shift register's current state and exposes that state as the module output.

The entire ParallelIn word is captured into DataOut on the active clock edge.

What happens when load is asserted?

DataOut <= ParallelIn;

Which RTL statement implements parallel loading?

All WIDTH bits are loaded together.

Why is the operation called a parallel load?

It is the complete candidate word to replace the current stored state when load is asserted.

What architectural role does ParallelIn serve?

Right Shift

The operation that moves every stored bit one position toward the least-significant side.

DataOut <= DataOut >> 1;

Which RTL statement implements the shift operation?

The current DataOut value is logically shifted right by one position and stored back into DataOut.

What happens when shift is asserted and load is not asserted?

Logical Right Shift

A right shift that introduces zeros into the newly vacated most-significant bit positions.

A zero.

What bit value enters the most-significant side when DataOut >> 1 performs the project's logical right shift?

The previous least-significant bit is discarded.

What happens to the old DataOut[0] during a one-bit logical right shift?

Old DataOut[i+1] becomes new DataOut[i].

How do the retained bits move during the right shift?

DataOut >> 1

What expression computes the shift register's candidate next state during a shift?

Because the next stored value is calculated from DataOut's current stored value.

Why does the shift operation depend on previous machine state?

The register's own current state is transformed and written back as its next state.

What feedback-like behavior occurs in DataOut <= DataOut >> 1;?

WIDTH

A parameter defining the number of bits stored and shifted by the module.

8

What is the default value of the WIDTH parameter?

No. WIDTH can be overridden when the module is instantiated.

Is the ShiftRegister permanently restricted to eight bits?

Parameterized Shift Register

A shift-register module whose stored-word width can be changed through a parameter without rewriting its core behavior.

[WIDTH - 1:0]

What range declares ParallelIn and DataOut as WIDTH-bit vectors?

Changing WIDTH consistently changes the width of ParallelIn, DataOut, the reset value, and the shift operation.

Why is parameterization useful in this ShiftRegister?

Width-Independent RTL

RTL written so the same module description remains valid for different parameter values.

{WIDTH{1'b0}}

What expression generates the reset value for DataOut?

Replication Operator

The Verilog {N{value}} construction that repeats a bit pattern N times.

WIDTH copies of 1'b0.

What does {WIDTH{1'b0}} generate?

An all-zero word exactly WIDTH bits wide.

What value is produced by {WIDTH{1'b0}}?

It automatically produces the correct number of reset bits for whatever WIDTH is selected.

Why is {WIDTH{1'b0}} preferable to hard-coding 8'b00000000 in this parameterized module?

Synchronous Reset

A reset whose effect is committed when the clocked always block is triggered by its active clock edge.

always @(posedge clk)

What event triggers the ShiftRegister's sequential logic?

At the positive edge of clk.

When can reset actually clear DataOut in this implementation?

Because reset is checked inside an always block sensitive only to posedge clk.

Why is this reset synchronous?

DataOut becomes an all-zero WIDTH-bit word.

What happens when reset is asserted at an active clock edge?

Reset Priority

The rule that reset overrides both load and shift when multiple control inputs are asserted together.

reset

Which ShiftRegister control has the highest priority?

DataOut is cleared to zero.

What happens if reset and load are both asserted on the same active edge?

DataOut is cleared to zero.

What happens if reset and shift are both asserted on the same active edge?

DataOut is cleared; neither loading nor shifting determines the new state.

What happens if reset, load, and shift are all asserted together?

Because the if (reset) branch is evaluated before the normal-operation else branch containing load and shift.

Why does reset override load and shift?

Load Priority

The rule that parallel loading overrides shifting when both normal-operation commands are asserted together.

load

Between load and shift, which control has higher priority?

ParallelIn is loaded into DataOut; no shift is performed for that edge.

What happens if load and shift are both asserted while reset is low?

Because the shift condition is reached only through the alternative path where load was not selected.

Why does load override shift in the RTL?

if (load) ... else if (shift)

What RTL structure establishes load-over-shift priority?

Priority Logic

Control logic in which simultaneous requests are resolved according to a predefined ordering rather than being treated equally.

reset → load → shift → hold

What is the complete priority order of the ShiftRegister?

The control priority defines which candidate next state wins when several state-changing requests occur during the same cycle.

Why is the order of the if statements architecturally meaningful?

A different ordering could produce a different stored value when multiple controls are asserted simultaneously.

Why is control priority part of the module's behavior rather than merely coding style?

Hold Behavior

The register's preservation of its current state when no higher-priority state-changing command is active.

DataOut retains its previous value.

What happens when reset = 0, load = 0, and shift = 0?

No assignment to DataOut occurs on that clock path, so the register naturally retains its stored value.

Why does DataOut hold without an explicit DataOut <= DataOut; statement?

Implicit Hold

A clocked-register behavior in which the previous value remains stored because no assignment occurs on the selected execution path.

No. A clock edge alone does not force DataOut to change; one of the state-changing control conditions must authorize a new value.

Does DataOut necessarily change on every positive clock edge?

reset, load, or shift

Which inputs can cause DataOut to receive a newly determined value at a clock edge?

The stored state remains unchanged.

What does a clock edge do when none of reset, load, or shift requests a state change?

Next-State Selection

The process of choosing which candidate value will become DataOut's next stored state according to reset/load/shift priority.

All zeros.

What is the candidate next state when reset is asserted?

ParallelIn.

What is the candidate next state when reset is low and load is asserted?

DataOut >> 1.

What is the candidate next state when reset and load are low but shift is asserted?

The current DataOut value.

What is effectively the next state when reset, load, and shift are all low?

DataOut_next = 0

What next-state equation applies when reset is asserted?

DataOut_next = ParallelIn

What next-state equation applies when reset = 0 and load = 1?

DataOut_next = DataOut >> 1

What next-state equation applies when reset = 0, load = 0, and shift = 1?

DataOut_next = DataOut

What next-state equation applies when reset = 0, load = 0, and shift = 0?

Priority-Based Next-State Function

The interpretation of the ShiftRegister as a register whose next value is selected from reset, parallel input, shifted current state, or held current state.

The controls determine which candidate next-state expression is allowed to reach the register.

How can the ShiftRegister be understood as a next-state selection problem?

A multiplexer-like next-state selection network feeding the DataOut register.

What hardware structure can the reset/load/shift decision conceptually imply before the register?

Control selects the transformation, while DataOut stores the resulting state.

How are control and storage responsibilities separated conceptually inside the ShiftRegister?

Load replaces the stored word with external data; shift transforms the word already stored.

What is the fundamental difference between load and shift?

External Replacement

Parallel loading replaces current state with a value supplied by ParallelIn.

Internal State Transformation

Shifting derives the next state from the register's own current state.

ParallelIn.

Which source supplies the new word during an external replacement?

DataOut's current state.

Which source supplies the information used during an internal shift transformation?

Load does not preserve the previous stored word; it replaces it with ParallelIn.

What happens to the previous DataOut value when a parallel load is committed?

A shift preserves most of the previous bits but changes their positions and discards the least-significant bit.

How does a shift differ from a complete replacement of state?

Controlled Spatial Transformation

The repositioning of remembered bits within a stored word under control of a sequential command.

Because the identities of the retained bits stay related to the old word while their bit positions change.

Why can shifting be described as a spatial transformation of stored data?

Binary Weight Repositioning

Changing a bit's position in a binary word, thereby changing the positional weight associated with that bit.

A right shift moves retained bits toward positions with lower binary weight.

How does a logical right shift affect the positional weights of retained bits?

For an unsigned binary value, a one-bit logical right shift corresponds to integer division by 2 with any fractional remainder discarded.

What arithmetic interpretation can DataOut >> 1 have for an unsigned value?

The shift register can reposition the next relevant bit for later processing while preserving the rest of the working word as state.

Why are shift registers useful in iterative arithmetic?

Serial/Parallel Conversion

Using shifting and parallel storage to move information between representations or interfaces with different transfer widths.

Arithmetic Alignment

Using shifts to reposition binary digits according to the weights required by an arithmetic operation.

Delay / Staging

Using sequential storage to preserve ordered information across successive clock cycles.

Bit-Stream Processing

Advancing stored information by one bit position per controlled step.

Serial/parallel conversion, arithmetic alignment, iterative arithmetic, delay/staging, and bit-stream processing.

What architectural uses for shift registers are identified in Part 08?

The stored word can be repositioned one controlled step at a time across successive clock cycles.

Why is a shift register naturally useful for bit-stream processing?

Each accepted shift produces a new stored state that becomes the source for the next accepted shift.

How can repeated shift commands create sequential data movement over time?

The word is captured simultaneously into DataOut rather than entering one bit at a time.

Why is the project's load operation specifically a parallel load?

DataOut = 8'b10110010.

If WIDTH = 8 and ParallelIn = 8'b10110010 when load is asserted, what value is stored after the active edge?

DataOut = 8'b01011001.

If DataOut = 8'b10110010 and a right shift occurs, what is DataOut after the edge?

DataOut = 8'b00101100.

If DataOut = 8'b01011001 and another right shift occurs, what value is stored afterward?

DataOut = ParallelIn.

If load = 1 and shift = 1 while reset = 0, what is the next DataOut?

DataOut = 0.

If reset = 1, load = 1, and shift = 1, what is the next DataOut?