Chapter 4 - COMPSCI 2GA3

What does a 2-input multiplexer do?

It selects one of two inputs based on a control signal: if s=0, output is x1

What is the main difference between combinational and sequential logic?

Combinational logic has no memory and output depends only on current inputs, while sequential logic includes memory and output depends on input history.

What is the function of a tri-state buffer when e=0?

The output is electrically disconnected from the input.

What basic element stores data in registers?

A D flip-flop stores a single bit of data and is the basic building block of a register.

What happens in a positive edge-triggered D flip-flop on a rising clock edge?

The value at the D input is stored and appears at the Q output after a delay.

How many D flip-flops are needed for an 8-bit register?

Eight D flip-flops are needed, one for each bit.

Why are tri-state buffers used with registers?

They allow multiple registers to share a data bus without conflict, as only one can enable output at a time.

What does the program counter (PC) do in instruction execution?

It points to the next instruction and is updated after each instruction is fetched.

What are the three types of RISC-V instructions discussed?

Arithmetic/logical (add, sub, and, or), memory reference (lw, sw), and control transfer (beq).

What is the purpose of multiplexers in a CPU datapath?

To select between multiple data sources for different instruction types.

What are the five stages of the RISC-V pipeline?

IF (Instruction Fetch), ID (Instruction Decode), EX (Execute), MEM (Memory Access), WB (Write Back).

What are structural, data, and control hazards in pipelining?

Structural: resource conflict, Data: dependency on previous instruction data, Control: uncertainty in control flow like branches.

What does forwarding (bypassing) in pipelining achieve?

It reduces stalls by using computed values directly instead of waiting for register write-back.

When can a load-use hazard not be avoided with forwarding?

When the required data from a load instruction is not yet available for the next instruction.

What is a pipeline "bubble"?

A cycle in which no useful work is done, usually due to a stall.

What is branch prediction and why is it important?

It predicts the outcome of branches to avoid pipeline stalls

What is dynamic branch prediction?

Hardware records actual branch history and predicts future behavior based on that history.

What is the purpose of the ALU control unit?

It determines the function the ALU performs based on instruction type and opcode.

What causes a control hazard?

A change in instruction flow, such as a branch, whose outcome is not yet known.

What is the function of the Main Control Unit in a CPU?

It generates control signals based on instruction opcodes to direct datapath behavior.

What is the critical path in a CPU?

The longest path that determines the minimum possible clock period, often through load instructions.

What is instruction-level parallelism (ILP)?

The ability to execute multiple instructions simultaneously to improve performance.

What is static multiple issue?

The compiler determines instruction groups to be issued together, minimizing hazards.

What is dynamic multiple issue (superscalar)?

The CPU dynamically selects and issues multiple instructions per cycle, resolving hazards at runtime.

What does register renaming help with?

It avoids data hazards by ensuring that different instructions using the same register name do not conflict.

What is speculative execution?

It executes instructions before it's certain they are needed, rolling back if the speculation is wrong.

How do you handle exceptions in a pipelined processor?

Flush the pipeline, save the PC and cause in SEPC and SCAUSE, and transfer control to an exception handler.

What does SEPC register store?

The program counter of the instruction that caused the exception.

What is SCAUSE in RISC-V?

A register that stores the reason or code for the exception or interrupt.

What happens during a BEQ instruction?

Registers are compared, and the PC is conditionally updated based on the result and offset.

What causes a stall on a branch?

Waiting for the branch decision before fetching the next instruction.

What is the role of pipeline registers?

They hold information passed between pipeline stages during each clock cycle.

What does a 2-bit branch predictor improve over 1-bit?

It avoids misprediction in nested loops by requiring two consecutive incorrect predictions to change direction.

What is a branch target buffer (BTB)?

A cache of branch target addresses used to fetch branch targets quickly.

What is the use of vectored interrupts?

They use different addresses for handlers based on the exception cause, reducing handler overhead.

What is a precise exception?

An exception that can be handled such that the program can be restarted correctly from the point it occurred.

What happens if multiple exceptions occur in a pipeline?

The earliest instruction’s exception is handled, and subsequent instructions are flushed.

What is the purpose of a reservation station in register renaming?

To temporarily hold operands and tags until an instruction is ready to execute.

What is the function of the reorder buffer (ROB)?

It ensures instructions commit in the correct order and handles register renaming results.

What is load speculation?

It predicts memory load values or addresses to execute loads early, rolling back if incorrect.

What is the key idea behind dynamic pipeline scheduling?

Instructions can execute out-of-order to avoid stalls but must commit results in order.

What is loop unrolling?

A compiler technique that replicates loop bodies to expose more instruction-level parallelism.

What are the advantages of dual-issue static scheduling?

Allows two instructions to be issued per cycle, improving throughput with careful hazard management.

Why do superscalar processors improve performance?

They issue and execute multiple instructions per cycle using dynamic scheduling and speculation.

What causes power inefficiency in advanced CPUs?

Complex techniques like speculation and dynamic scheduling increase power usage.

What is a power-efficient alternative to deep pipelines?

Using multiple simpler cores instead of complex single-core designs.

What is the role of the instruction decoder?

It interprets the fetched instruction and sets control signals for execution.

Why is it important to balance pipeline stages?

To maximize throughput and prevent slow stages from becoming bottlenecks.

How is speedup from pipelining calculated?

Speedup = Time between instructions (unpipelined) / Time between instructions (pipelined).

Why do all RISC-V instructions have the same length?

To simplify instruction fetching and decoding, aiding pipelining.

What is the main idea of forwarding in a pipelined processor?

To use computed values immediately from intermediate pipeline stages instead of waiting for write-back.

What are ForwardA and ForwardB signals used for?

To control multiplexers that select ALU input sources to resolve data hazards via forwarding.

What does a forwarding condition of ForwardA=10 mean?

The first ALU operand should come from the EX/MEM pipeline stage.

How do you detect a load-use data hazard?

By checking if the ID/EX.MemRead is set and if its destination register matches the source registers in the next instruction.

What happens when a load-use hazard is detected?

The pipeline is stalled, a bubble is inserted, and instruction fetch is repeated.

What is the purpose of stalling the pipeline?

To delay execution until data hazards or control decisions are resolved, ensuring correct operation.

What are the inputs of the ALU control function?

Opcode fields such as ALUOp, function7, and function3 determine the ALU operation.

Why can't wires in the datapath be joined freely?

It causes data conflicts

What is the main use of the MEM/WB pipeline register?

To store results from memory or ALU before they are written back to the register file.

What does an edge-triggered state element do?

It updates stored data only on a rising or falling edge of the clock.

How does a register with write control work?

It only updates its stored value on a clock edge if the write enable signal is active.

What is the significance of cycle time in pipeline performance?

Shorter cycle time allows faster instruction execution

What is the function of the datapath in the CPU?

To process and move data through units like ALU, registers, and memory.

How is ALU control derived for R-type instructions?

By decoding both function3 and function7 fields in conjunction with ALUOp.

Why is memory separated in pipelined processors?

To avoid structural hazards by allowing simultaneous instruction fetch and data access.

What does an instruction fetch stage do?

Retrieves the instruction pointed to by the program counter (PC).

What happens in the decode stage (ID)?

Registers are read and the instruction type is determined by the control unit.

What is the function of the execute stage (EX)?

Performs arithmetic or address calculations using the ALU.

What is the role of the memory stage (MEM)?

Performs memory access operations like load and store.

What is the purpose of the write-back stage (WB)?

Writes the result of an instruction back into the register file.

What is the hazard if a needed register value is not yet written?

A data hazard, which may require forwarding or stalling.

What is the function of the control unit in pipelining?

Generates appropriate control signals for each pipeline stage based on instruction type.

How are pipeline stages isolated from one another?

By inserting pipeline registers between them to store intermediate data.

Why is it important for the D input to remain stable around the clock edge in a flip-flop?

To ensure correct data is stored and avoid metastability.

Why are enable signals used in flip-flops and registers?

To control when the register should accept and store new data.

What is the purpose of a multiplexer (MUX) in the datapath?

It selects one of multiple inputs to pass through to the output based on control signals.

How is the branch target address calculated in BEQ instructions?

By sign-extending the displacement, shifting left by one, and adding to the current PC.

What does Zero output from ALU indicate in a BEQ?

That the two compared registers are equal, which may trigger a branch.

Why can't a value be forwarded backward in time?

Because the needed value hasn’t been computed yet, such as in a load-use hazard.

What is early restart in cache miss handling?

The CPU restarts execution before the entire block is loaded, using the first available word.

Why do we need separate instruction and data memories in pipelining?

To allow concurrent access and avoid structural hazards.

What happens in a pipelined R-type instruction execution?

Registers are read, ALU performs computation, and result is written back in 5 stages.

What are pipeline bubbles used for?

To handle hazards by inserting idle cycles into the pipeline.

What does critical-word-first mean?

Load the word needed by the CPU first during a memory block fetch.

What is the goal of Instruction-Level Parallelism (ILP)?

To increase CPU throughput by executing multiple instructions simultaneously.

What does the MEM/WB.RegWrite signal control?

Whether the register file will be updated with the result in the write-back stage.

How are exceptions handled in the pipeline?

Flush instructions, save PC and cause, then jump to exception handler.

Why are imprecise exceptions hard to handle?

They don’t preserve the exact point of failure, making it harder to recover or restart.

What is dynamic scheduling in CPU?

Out-of-order execution of instructions to improve throughput while maintaining correct final state.

Why is latency not reduced by pipelining?

Each instruction still takes the same total time to complete

How is a data hazard from a register write handled in a pipeline?

By forwarding the result or stalling until the write is completed.

What is the speedup of a pipeline with balanced stages?

The speedup approaches the number of pipeline stages.

What is a superscalar processor?

A CPU that can issue and execute multiple instructions per clock cycle.

What makes multiple-issue CPUs more complex?

Hazard detection, instruction scheduling, and power requirements increase significantly.

What is the impact of pipeline hazards on performance?

They introduce stalls and reduce effective instruction throughput.

How does a compiler reduce pipeline stalls?

By reordering instructions to avoid hazards (code scheduling).

What are the benefits of register renaming?

Eliminates false dependencies and increases parallel execution opportunities.

What does a stall do to the PC and IF/ID registers?

It prevents them from updating, effectively pausing the pipeline.

What is the goal of the pipelined datapath design?

To improve instruction throughput by overlapping stages of multiple instructions.