CPC - Hardware

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48 Terms

1
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What did Von Neumann realize about data & programs?

They are indistinguishable and can use the same memory.

2
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What kind of processor does Von Neumann architecture use?

A single processor.

3
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What is the sequence of operations in Von Neumann architecture?

Fetch – Decode – Execute.

4
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What component stores small amounts of data for fast access?

Registers.

5
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What are registers?

Smallest unit of storage; allow fast data transfer.

6
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What are General Purpose Registers used for?

Temporarily store data values and processed results.

7
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What are Special Purpose Registers?

Registers with a particular function (e.g. PC, MDR, MAR).

8
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What does the Program Counter (PC) do?

Holds the address of the next instruction to fetch.

9
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What does the Memory Data Register (MDR) do?

Holds data fetched from memory.

10
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What does the Memory Address Register (MAR) do?

Holds the address of the memory cell to be accessed.

11
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What does the Accumulator (ACC) do?

Holds values being processed by arithmetic/logical operations.

12
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What does the Index Register (IX) do?

Stores a value to modify an address (indexed addressing).

13
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What does the Current Instruction Register (CIR) do?

Holds the fetched instruction for decoding/execution.

14
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What does the Status Register do?

Holds results of comparisons, errors, or intermediate arithmetic results.

15
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What does the Arithmetic & Logic Unit (ALU) do?

Performs arithmetic & logical operations.

16
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What does the Control Unit (CU) do?

Fetches, decodes, and directs execution of instructions.

17
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What is Immediate Access Store (IAS)?

Memory directly accessible by the processor.

18
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What is the system clock?

Synchronizes all components using timing pulses.

19
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What are buses?

Parallel wires for data transfer between computer components.

20
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What does the Data Bus do?

Bidirectional, carries data/instructions.

21
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What does the Address Bus do?

Unidirectional, carries memory addresses.

22
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What does the Control Bus do?

Bidirectional, transmits control signals.

23
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What is clock speed?

Number of pulses per second (measured in GHz).

24
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How does increasing clock speed affect performance?

Increases performance, but limited by heat generation.

25
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What is bus width?

Number of lines in a bus; affects simultaneous data transfer.

26
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How does bus width affect performance?

Wider bus = more bits transferred at once = higher speed.

27
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What is cache memory?

Stores frequently used instructions for faster CPU access.

28
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How does increasing cache size affect performance?

Reduces CPU wait time, increases performance.

29
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What does number of cores mean?

Number of processors in a CPU chip; more cores = multitasking = better performance.

30
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What is a port?

Hardware interface between CPU/device & peripherals.

31
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What does USB port do?

Connects both input and output devices.

32
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What does HDMI port do?

Connects output devices (e.g. monitors), carries audio & video.

33
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What does VGA port do?

Connects output devices (video only, no audio).

34
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What does the PC do during fetch?

Holds the address of next instruction.

35
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What happens to PC during fetch?

PC address copied to MAR, PC incremented.

36
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Where is the instruction loaded from and to?

Loaded from memory to MDR, then to CIR.

37
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What happens during decode?

Opcode and operand are identified.

38
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What happens during execute?

CU sends signals to carry out instruction.

39
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What does "MAR ← [PC]" mean?

Copy value from PC to MAR.

40
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What does "PC ← [PC] + 1" mean?

Increment PC by 1.

41
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What does "MDR ← [[MAR]]" mean?

Load value from memory at address in MAR into MDR.

42
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What does "CIR ← [MDR]" mean?

Copy value from MDR to CIR.

43
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What do square brackets [ ] mean?

Value currently in register.

44
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What do double square brackets [[ ]] mean?

Value stored at the address in the register.

45
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What is an interrupt?

A signal seeking processor's attention.

46
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When are interrupts checked?

At end of F-E cycle for current instruction.

47
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What happens if interrupt is high priority?

Registers saved on stack, PC loaded with ISR address, ISR executed, then registers restored and execution resumes.

48
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