Thẻ ghi nhớ: CEA FE | Quizlet

I. Which of the following statements is part of the Von Newmann principle?

A. The computer uses a program counter to indicate the location of the next statement B Computer can control all operations with a single program

C. Computer memory is not addressable

D. Each instruction must have a memory area containing the address of the next instruction

A

2. What is the distinction between Computer Architecture and Computer Organization? A Computer Architecture IS the way the system is structured while Computer Organization is those attributes of a system that are visible to the user

B. Computer Architecture is those attributes of a system that are visible to the user, while Computer Organization is the way the system is structured

C Computer Architecture and Computer Organization are the same

D Computer Architecture is slower than Computer Organization

A

3. Which of the following are the four basic functions that a computer performs?

A. Data processing Data storage Data movement Control

B. Data processing Data storage Data movement Interrupt C Data processing Data storage, Interrupt Control

D. Data processing Interrupt, Data movement Control

A

4. Which one of four basic functions of computer describes the following statement? "The paths among components are used to move data from memory to memory and from memory through

gates to memory".

A. Data storage

B Data processing

C. Data movement

D Control

C

5. During the development process of the computer, which of the following statements is false?

A. The second generation uses transistors

B. The first generation uses vacuum tubes

C The fourth generation uses integrated circuit

D. The third generation uses transistor

D

6. What electronic component is used to govern operations such as fetching decoding and performing arithmetic operations executed by a processor?

A Using a system clock

B. Using a quartz crystal

C Using a analog to digital converter

D. Using a counter

A

7. The pulse rate in the ck system is known as the _

A. ck cycle

B. ck speed

C ck time

D ck tick

B

8. Which register is the memory address register?

A.MAR

B.MBR

C.IR

D.PC

A

9. Which representation IS most efficient to perform arithmetic operations on the signed integer numbers?

A. Sign-magnitude

B 2's complement

C l's & 2'scompliment

D l's complement

B

IO. What is true about IAS Memory Formats?

A. The memory of the LAS consists of I000 storage locations (called words) of 32 bits each

B. Only data is stored in the memory

C Both data and instructions are stored in the memory

D. Only instructions are stored in the memory

C

11. What is the most important characteristic of the Synchronous Bus?

A Data IS transmitted at the same time

B. The occurrence of one event on a bus follows and depends on the occurrence of a previous event

C The occurrence of events on the bus is determined by a clock

D. No common clock signal controlling operation

C

12. Which of the following memory devices has the lowest access speed?

A.ROM

B. Flash memory

C.Magnetic tape

D.HDD

E. Cache

C

13. Consider an expression: NOT (1111 1010) What is the result of this expression?

A. 0000 1010

B. 0000 0101

C 1111 0101

D. 1111 1010

B

14. What is the primary purpose of cache memory in a computer system?

A. To store frequently used data for quick access

B. To store the operating system

C To store user files and documents

D. To store the CPU registers

A

15. A set-associative cache consists of 64 lines divided into four-line sets 2"19-words main memory contains 4K blocks of 128 words each How many bits are there in the tag field of the cache?

A.5

B.6

C.7

D.8

E.9

D

16. Why IS cache design used in high-performance computing (HPC)? (Choose three correct answers)

A. Because there is a significant speed gap between the processor and the internal memory in HPC.

B Because applications in HPC often require a large bandwidth to support intensive data processmg

C Because power consumption can be a significant operational cost in HPO environments

D. Because multiple processors are often working in parallel, caches provide a way to efficiently manage data

required by these processors

ABD

17. How many bytes of data does each sector in the Winchester hard drive disk have? A 128 bytes

B. 256 bytes

C 512 bytes

D. 1024 bytes

E. 4096 bytes

C

18. Using Hamming Code with one error corection to store an 12-bit word in memory, the stored word

111001001101 consists of 8 bits data and 4 bit bits parity check What are the parity bits?

A.0110

B. 0111

C 1110

D 0101

E. None of the mentioned

D

19. What is correct about increasing performance and endurance?

A. Hard Disk-DRAM-NAND Flash-SRAM

B. Hard Disk-NAND Flash-DRAM - SRAM

C. NAND Flash-Hard Disk-SRAM-DRAM

D. Hard Disk - DRAM -NAND Flash-SRAM

B

20. With the hard disk data layout, the sel of all the tracks in the same relative position on the platter, is called

A. Cylinder

B. Tracks

c Inter-track gap D Sector

A

21. Consider a 5-drive, 200 GBytes-per-drive RAID array What is the available data storage capacity for each of

the RAID levels 5?

A 200 GBytes

B. 400 GBytes

C 600 GBytes

D. 800 GBytes

E. None of the mentioned

D

22. Consider a 5-drive, 100 GByles-per-drive RAID array. What is the available data storage capacity for each of

the RAID levels 5?

A 400 GBytes

B. 200 GBytes

C 300 GBytes

D. 500 GBytes

A

23. What is incorrect about SSDs have the following advantages over HDDs?

A. Higher access times and latency rates Over IO times slower than the HDD

B Durability: Less susceptible to physical shock and vibration

C Longer lifespan SSDs are not susceptible to mechanical wear

D Lower power consumption SSDs use considerably less power than comparable-size HDDs

E. Quieter and cooler running capabilities Less space required lower energy costs and a greener enterprise

A

24. Which registers can interact with the secondary storage?

A.MAR

B.PC

C.IR

D.RO

E. All of the mentioned

A

25. Consider an expression: A. (B.C)

What expression is equal to the given expression?

A(A+B)(A+C)

B.(A+B).C

C.A (B+C)

D. NOT (A.(B+C))

A

26. Determine the address of the next instruction to be executed Usually, this involves adding a food number to the address of the previous instruction

A Instruction fetch

B. Instruction operation decoding

C Instruction address calculation

D Operand fetch

E. Operand address calculation

C

27. For interrupts, all 1/0 modules share a common interrupt request line. When the processor senses an interrupt, it sends out an interrupt acknowledge. This signal propagates through a series of 1/0 modules until it gets to a requesting module.

Which kind of interrupt technique is it?

A. Multiple interrupt lines

B Software poll

C. Daisy chain

D. Bus arbitration

C

28. What role does an Application Programming Interface (API) play in software development?

A. It allows program access to hardware resources using high-level language libraries

B. It defines low-level machine instructions

C It provides a standard for binary portability

D. It manages system resources for the operating system and machine language instructions

A

29. Which state indicates that a process is currently being executed by the processor?

A. Running

B. Ready

C. NewBorn

D. Halted

A

30. Which state indicates that a process is currently being executed by the processor?

A. Running

B Ready

C NewBorn

D. Halted

A

31. The task of subdivision is carried out dynamically by the os and is known as

?

A. Scheduling

B. Memory management

C Virtual Memory

D. All of the mentioned

B

32. Which of the following statements is incorrect about Translation Look-aside Butter (TLB)?

A. The use ofTLB eliminates the need for keeping a page table in memory

B TLB only maintains a subset of the entries stored in the full memory-based page table

C When there is a TLB miss the system needs to access the page table

D A translation lookaside butter (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory

A

33. (RI) =011IOI IO, (R2) = I IOI1111, the result of (RI) XOR (R2) is

A. 11011011

B. 00010110

C 10101001

D. 11001101

C

34. What is the output of a NOT gate when the input is 0?

A. 0

B 1

C Undefined

D.2

B

35. Express an integer number+ 18 (using 8-bits length) in two's complement representation.

A. 00010010

B. 10010010

C 00001101

D. 10011101

A

36. Which registers can be assigned to a variety of functions by the programmer?

A. Data registers

B. General purpose registers

C Address registers

D Condition codes (flags)

B

37. What are the most important general categories of data that machine instructions operate on?

A. Addresses, numbers characters, and logical data

B Text, images, and audio

C Variables functions and arrays

D Instructions, control signals, and registers

A

38. What is the output of Left Shift Operator<< on (00011000<<2)?

A. 01100000

B 11000000

C 00000110

D 00000011

A

39. Which addressing mode allows direct specification of the memory address within the instruction?

A. Direct

B Indirect

C Register Indirect

D Displacement

A

40. Which of the following PDP series computers is known for its use of 12-bit instructions and a single general-purpose register, the accumulator?

A PDP-8

B. PDP-IO

C PDP-11

D. PDP-6

A

41. In MASM32 which command is incorrect?

A. ADDEAX, a

B. ADD EAX, EBX

C ADDa, EAX

D. ADD a, b

D

42. What is the primary function of the Arithmetic and Logic Unit (ALU) in a processor?

A. Perform actual computations and data processing

B. Control the movement of data and instructions

C. Act as an interface to the system bus D Manage the internal processor memory

A

43. The PC IR, MAR MBR registers belong to which of the following groups?

A. Control and Status Registers

B. User-Visible Registers

C. General Registers

D Handle Registers

A

44. When considering the number of pipeline stages what trade-offs must be made in computer architecture?

A. Trade-offs between potential speedup and increased cost and delays

B. Trade-offs between software and hardware

C. Trade-offs between speed and efficiency

D Trade-offs between branching and executing instructions with conditions

A

45. What does CISC stand for?

A. Complex Instruction Set Computer

B. Computer Instruction Set Complex

C. Complex Instruction Summarize Computer

D Computer Instruction Summarize Complex

A

46. What is one of the advantages of using a register file in computer architecture?

A. Reduction in memory accesses, saving time

B. More efficient use of space due to dynamic adaptation

C. Efficient handling of both local and global variables

D Easier management of cache residency

A

47. How does pipelining in a RISC architecture handle branch instruction?

A. By using NOOP instructions inserted by the compiler or assembler

B. By eliminating branch instructions from the instruction stream

C. By executing branch instructions in a separate pipeline

D By delaying all instructions until branch instructions are executed

A

48. is (are) determined by the number of instructions that can be fetched and executed at

the same time (the number of parallel pipelines) and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions

A. Instruction-level parallelism

B. Machine parallelism

C Both instruction-level parallelism and machine parallelism

D None of the mentioned

A

49. Which is the correct choice for the description "A single machine instruction controls the simultaneous execution of a number of processing elements such as vector and array processors"?

A Single instruction, single data (SISD)

B. Single instruction multiple data (SIMD)

C. Multiple instruction, single data (MISD)

D Multiple instruction multiple data (MIMD)

B

50. What is one advantage of Nonuniform Memory Access (NUMA) over Uniform Memory Access (UMA)?

A. NUMA provides each processor with its own local memory, reducing memory access times

B. NUMA allows all processors to access the same memory location simultaneously

C. NUMA is easier to implement than UMA

D NUMA provides limited memory capacity

A

51. What is the most common mapping technique used in cache memory in modern computers?

A. Direct Mapping

B. Fully Associative

C Set Associative

D None of the mentioned

C

52. Which of the following components was used in the first ENIAC computer?

A. Bipolar transistors

B. Field transistors

C.Vacuum tubes

D. Semiconductor Ics

C

53. Which of the following statements IS true for Von Neumann architecture?

A. Shared bus between the program memory and data memory

B. Separate bus between the program memory and data memory

C External bus for program memory and data memory

D External bus for data memory only

A

54. Which of the following component does not belong to central processing unit?

A. System interconnection

B. Arithmetic and logic unit

C Registers

D. Control unit

E. CPU interconnection

A

55. Central processing unit (CPU) oflAS computer consists of

A. Main memory and ALU (arithmetic and logic unit)

B. ALU (Arithmetic and Logic Unit) and CU (Control Unit) CCU (Control Unit) and IO Module

D. ALU (Arithmetic and Logic Unit) and IO Module

B

56. The first generation of computers used fodrigital logic elements and memory?

A. Transistor

B. Integrated Circuits

C Large-scale integration

D. Vacuum Tubes

D

57. In the computer what categories do external devices include? (choose 3 correct answers)

A. Human readable

B Communication

C Data Conversion

D. Machine readable

ABD

58. Which of the following determines the Bus Width?

A. The clock speed of the CPU

B. The number of cores in the processor C The size of the motherboard

D. The number of parallel lines in the data bus

E. Number of components connected to Bus

D

59. In the CPU, what is the functionality of the control unit?A. To decode program instructions

B. To controls the sequence of operations

C To store program instructions

D To transfer data to primary storage

B

60. The basic components of a computer are

A. Main memory, CPU, VO modules and system interconnection

B. Main memory, CPU, VO modules and Storage device

C Main Memory CPU Peripherals and Storage device

D. Main memory, CPU, 1/0 modules and Storage device

A

61. What is the correct order of memory access speed from fastest to slowest?

A Registers> Cache> RAM> SSD

B. Cache> Registers >RAM>SSD

C Registers> Cache >SSD > RAM

D. Cache> Registers >SSD > RAM

E. All of the mentioned are wrong

A

62. What is the cache memory level that is integrated into the processor chip and has the lowest latency?

A. Ll cache

B. L2 cacho

C L3 cache

D. L4 cache

A

63. Which of the following components of CPU is responsible to direct the system to execute instructions?

A Arithmetic and Logic Unit (ALU)

B. Control Unit (CU)

C Registers

D. Random Access Memory (RAM)

B

64. Consider a machine with a byte addressable main memory of 2 16 bytes and block size of 8 bytes Assume that a direct mapped cache consisting of 32 lines is used with this machine. How many bits are there in the line field of the cache?

A. 3

B 4

C. 5

D6

E. 7

C

65. For reads to and writes from main memory, translates each virtual address into a physical address in main memory.

A.MAR

B.MMU

C Overlays

D.TLB

E. Accumulator

B

66. What is the main idea of using Hamming code for error correction?

A. Adding extra parity bits to the data bits such that the number of Is in each subset of bits is even

B. Adding extra parity bits to the data bits such that the number of Is in each subset of bits is odd

C Adding extra parity bits to the data bits such that the parity bits form a binary number indicating the position

of the error bit

D Adding extra parity bits to the data bits such that the parity bits form a binary number indicating

C

67. What are the key differences in the architecture of NOR and NAND flash memory?

A. NOR flash memory cells are connected in series, while NAND flash memory cells are connected in parallel

B. NOR flash memory cells are connected in parallel while NAND flash memory cells are connected in series

C Both NOR and NAND flash memory cells are connected in series

D. Both NOR and NAND flash memory cells are connected in parallel

E. All of the mentioned are wrong

B

68. Which memory has the fastest speed and smallest capacity?

A. Cache

B. Main memory

C HDD

D Magnetic Disk

A

69. is a set of physical disk drives viewed by the operating system as a single logical drive

A.CLY

B. SSD

CRAID

D.CAV

C

70. Sort the following memory types in ascending order by access speed

A HDD-Main Memory-L2 cache-LI cache

B. HDD-Main Memory-LI cache-L2 cache

C HDD-12 cache-LI cache-Main Memory

D. Main Memory-L2 cache-LI cache-HDD

A

71. Which IS the correct choice for sorting in increasing speed average of memory?

A. SSD O Main Memory O Cache Memory I Magnetic Tape

B Magnetic Tape : SSD D Cache Memory O Main Memory

C Magnetic Disk SSD D Cache Memory 1 Main Memory

D Magnetic Disk I Magnetic Tape O Main Memory I Cache Memory

E Magnetic Disk ISSD O Main Memory O Cache Memory

E

72. For the following Boolean expressions AB+ AB' and the truth table AB B' output

1 0 1 ?

1 1 0 ?

0 0 1 ?

0 1 0 ?

Choose the correct option to replace at "?" (order top to bottom)

A. 1,1,1,0

B 1,1,1,1

C. 1,0,1,0

D. 0,1,1,0

(Suggest 1 1 0 0)

74. If you have a boolean function with 3 variables how may rows are there in the truth table?

A. 8 rows

B. 3 rows

C 6rows

D.12 rows

A

75. ln isolated I/O,

A The I/O devices and the memory share the same address space

B. The I/ 0 devices have a separate address space from memory

C The memory and 1/0 devices have an associated address space

D. A part of the memory is specifically set aside for the 1/0 operation

E. None of the mentioned

B

76. Which component defines the system call interface to the operating system and facilitates binary portability?

A. Application Binary Interface

B Application Programming Interface

C Instruction Set Architecture

D Central Processing Unit

A

77. What is the initial state of a process when 4 is admitted by the high-level scheduler, but not yet ready to execute?

A.New

B. Ready

CRunning

D Halted

A

78. The chunks of a program, known as pages, could be assigned to available chunks of memory, known as

frames, IS called

A. Swapping

B. Partitioning

C Paging

D Virtual Memory

E. Segmentation

C

79. How does Boolean algebra contribute to the design of digital circuits?

A. It simplifies the implementation of desired functions

B. It helps in the analysis of economic data

C It facilitates the design of analog circuits

D. It is primarily used for chemical engineering and physical engineering

A

80. When both inputs are 1. what is the result of a NAND gate?

A.0

B. 1

C 2

D Undefined

E.#NA

A

81. Express a sign integer number (+18) in the sign magnitude representation

A. 00010010

B. 10010010

C 11110010

D 01110010

A

82. Why IS it essential to use symbolic representation of machine instructions?

A. It makes machine instructions more human-readable and understandable

B. It reduces the overall complexity of computer systems and user programs

C It minimizes the need for memory storage for the user programs

D It enables fastest execution of high level language instructions

A

83. The hardware mechanism that allows a device to notify the CPU is called

A. polling

B. interrupt

C driver

D. controlling

B

84. What is a branch instrtuction?

A. The intructions that are used to divide a program into multiple subprograms

B The intructions that have as one of its operands the address of the next instruction to be executed

C The intructions that are used to pause the program

D. The intructions that are used to return to the beginning of the program

B

85. The effective address of______ is

EA =A + (R)

A. relative addressing

B autoindexing

C postindexing

D preindexing

B

86. ln MASM32, which OPCODE is used to compare two values?

A.COM

B. CMP

C IF... ELSE

D.TEST

B

87. What is the role of the control unit in a processor?

A. The control unit's primary role is to perform arithmetic and logical operations within the processor, orchestrating the manipulation of data

B. The control unit only manages the flow of data between the CPU and external devices and

does not play a significant role in executing instructions

C The control unit is solely responsible for managing the flow of instructions from secondary storage to RAM and does not have a role in the internal operation of the CPU

D. The control unit in a processor directs and coordinates the

D

88. How do data registers and address registers differ in some computer systems?

A. Address registers can be employed in calculating operand addresses, while data registers hold data

B. Data registers are only used for stack-related operations

C Data registers are used for indexed addressing while address registers are used for data storage

D. Address registers are reserved for segmented addressing while data registers are general-purpose

A

89. What is the main benefit of using ARM processors over other processors?

A Low cost and low power consumption

B. Higher degree of multi-tasking

C Lower error or glitches

D. Efficient memory management

A

90. Which statement is incorrect about RISC and CISC architecture?

A. CISC architecture is more convenient for programmers than RISC architecture.

B CISO architecture has more operands in a intruction compared to RISO architecture

C CISC architecture has a more flexible instruction set than RISC architecture

D CISC architecture requires more general-purpose registers than RISC architecture

D

91. In the concept of Register Windows, how many register groups are there?

A. 4

B3

C2

D No distinction

B

92. What is the main benefit of using RISC over CISC?

A. RISC has more instructions and addressing modes than CISC

B. RISC has faster instruction execution and simpler instruction decoding than CISC

C RISC has variable-length instruction formats and direct memory access than CISC

D. RISC has more registers and pipelines than CISC

B

93. What is the benefit of using a superscalar organization over a scalar organization?

A. It increases the instruction throughput and improves the performance

B It reduces the power consumption and the heat dissipation

C It simplifies the instruction set and the compiler design

D All of the mentioned

E None of the mentioned

A

94. What does the term "instruction-level parallelism" refer to in computer architecture?

A. The degree to which instructions in a program can be executed in parallel

B. The number of processor cores in a multi-core CPU with multiple resources

C The complexity of the instruction set architecture

D. The length of an instruction cycle with high level programing language

A

95. To enhance performance in a superscalar processor, which method(s) should we apply?

A. Duplication of resources

B Out-of-order issue

C Renaming registers

D All of the mentioned

D

96. How many common classifications of parallel systems are there as proposed by Flynn?

A. 2

B3

C4

D5

C

97. Which write technique in which all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid.

A. Write through

B. Write back

C. Write around

D. No write allocate

A

98. How does multithreading improve the performance of a processor?

A. II increases the instruction-level parallelism by issuing multiple instructions from different threads in the same cycle

B. it increases the thread-level parallelism by executing multiple threads on different cores or

processors

C It increases the utilization of the processor resources by hiding the latency of long-latency events such as cache misses or branch mispredictions

D. All of the mentioned

D

99. Follow the Amdahl's law for multiprocessors if only 10% of the code is inherently serial (f=0.9), running the program on a multicore system with 4 processors, a performance gain (speedup factor) would be

A. 307%

B. 297%

C. 317%

D. 327%

A

I00.What is the significance of the program counter (PC) in the fetch phase of the instruction cycle?

A. The program counter (PC) IS not used in the fetch phase, and its role IS limited to tracking the number of instructions executed by the CPU

B. The program counter (PC) in the fetch phase holds the memory address of the next instruction to be fetched and executed

C. The program counter (PC) is responsible for executing instructions and has no specific role during the fetch phase

D. The program counter (PC) is only relevant in multi-core processors and does not contribute

B

IOI.The register file employs much shorter addresses than addresses for cache and memory.

A. True

B. False

A