com sys prefinals

Computer Bus

communication pathway that connects two or more devices or modules used for transferring data

Address bus

unidirectional bus that transports memory addresses

Data bus

bidirectional bus that transfers instructions coming from or going to the processor

Control bus

bidirectional bus that transports orders and synchronization signals

Serial transmission

data bits are sent one by one in a medium

Parallel transmission

multiple data bits are transmitted over multiple channels at the same time

Synchronous protocol

data bits are transmitted as a continuous stream in time with a master clock

Asynchronous protocol

data bits can be sent at any point in time using start and stop bits

Bus arbitration

process by which multiple requests are recognized and priority is given to one

Centralized arbitration

single hardware device controls allocation of bus access

Distributed arbitration

each module participates in the arbitration process without a central controller

Chipset

component that routes data between a computer’s buses

Northbridge

controls transfer of data between processor and RAM

Southbridge

handles communication between peripheral devices

Front-Side Bus

internal bus that allows processor communication with RAM

Expansion Bus

allows motherboard components to communicate with one another

Industry Standard Architecture

IBM bus with 8-bit data bus and 20 address lines

VESA

standard interface between a computer and its expansion

Accelerated Graphics Port

bus connected to CPU for fast video processing

Peripheral Component Interconnect

Intel-developed bus with 32- or 64-bit architecture

Small Computer Systems Interface

standard electronic interface for faster peripheral communication

PCMCIA

standard bus for laptop computers using 68-pin connector

PCI Express

interface standard for connecting high-speed components

Universal Serial Bus

interface for connecting peripheral devices with plug-and-play support

Plug-and-play

operating system automatically configures peripheral devices

Hot-swapping

removal and replacement of peripherals without rebooting

I/O Architecture

system responsible for input, output, and connection to the outside world

Input peripherals

devices that allow user input to the computer

Output peripherals

devices that allow information output from the computer

Input-output peripherals

devices that allow both input and output operations

Storage devices

devices used for storing and fetching information

Data rate

amount of data transferred in a period of time

I/O bandwidth

amount of information communicated per unit time

I/O response time

total elapsed time to accomplish an input or output operation

Programmed I/O

mode where CPU constantly monitors peripherals during transfer

Interrupt Initiated I/O

mode where peripherals generate interrupt signals for CPU attention

Direct Memory Access

technique allowing peripherals to transfer data directly to memory

Buffer Chaining

DMA method handling multiple transfers using linked list of buffers

Operation Chaining

DMA method executing successive commands automatically

I/O Controller

intermediary interface between CPU and peripheral devices

Interface translation

function of converting connection protocols and signals

Addressing

process of handling memory locations for processing

Multiplexing

combining multiple signals over a bus

Buffering

preloading data into memory before processing

Error detection and correction

function for detecting and correcting errors

Device driver

software that allows operating system to communicate with hardware