Memory Mapped IO used for GPIO Lecture Notes

Practice flashcards covering Memory Mapped I/O, peripheral access (GPIO), specific microcontroller memory maps (RP2040, STM32U545), and the Rust embedded implementation stack.

What does the acronym MMIO stand for?

Memory Mapped Input Output

According to the transcript, which component asks for a data transfer on the bus?

The Memory Controller

In the RP2040 example, what is the address space size and the base address for the SIO Registers?

The address space is $4GB$ and the SIO Registers base address is $0xd000\_0000$

For the STM32U545RE example, what is the base address for GPIO?

$$0x4202\_0000$$

What is the address range for the Private Peripheral Bus (PPB) in the Cortex-M33 memory layout?

$0xE0000000$ to $0xE00FFFFF$

What is the specific address for the SysTick Timer in the Cortex-M33 layout?

$$0xE000E010$$

What are the two common examples of System Control Registers and their actual addresses?

SYST_CSR at $0xe000\_e010$ and CPUID at $0xe000\_ed00$

Why might writing several values to the same memory address via a compiler result in only the last value being stored?

Compilers optimize code and do not know that a memory address represents a peripheral register like UART_TX

Which Rust functions should be used to avoid compiler optimization when reading from or writing to registers?

read_volatile and write_volatile

What is the difference between write-through and write-back cache?

In write-through, data is written to the cache and main memory simultaneously; in write-back, data is written to the cache and later to main memory

In chips that use cache, how is the Memory Mapped I/O region typically handled to ensure correct peripheral operation?

The MMIO region is set as nocache, or the cache must be flushed before a volatile_read and after a volatile_write

What is the register offset for the CPUID Register?

$$0xed00$$

In the CPUID register bit manipulation example, how many bits are shifted and masked to retrieve the variant?

Shift right $20$ bits and keep only the last $4$ bits ($0b1111$)

What does the acronym AIRCR stand for?

Application Interrupt and Reset Control Register

What is the bit position (POS) for VECTKEY and SYSRESETREQ in the AIRCR register according to the transcript code?

VECTKEY_POS is $16$ and SYSRESETREQ_POS is $2$

What is the VECTKEY value required to write to the AIRCR register fields?

$$0x05fa$$

What does an SVD XML file describe?

System View Description, which defines names, base addresses, registers, offsets, and field bit ranges for a device

What are the three peripherals involved in connecting RP2040 GPIO pins to the processor?

PAD, IO Bank (GPIO), and SIO

What is the function of the SIO peripheral on the RP2040 regarding GPIO?

Single Cycle Input/Output, able to set the pin as Input or Output and control common pin values

What is the function of the IO Bank (GPIO) peripheral on the RP2040?

It multiplexes the functions of the GPIO pins using the MUX function (F5 for SIO)

Which SIO register is used to read the input value of GPIO pins on the RP2040?

GPIO_IN

What is the address for GPIO_OE on the RP2040 SIO?

$$0xd000\_0020$$

Which SIO register on the RP2040 is used to set the Output Enable bit for a specific pin to 0 (input)?

GPIO_OE_CLR ($0xd000\_0028$)

What are the addresses for GPIO_OUT_SET and GPIO_OUT_CLR on the RP2040?

GPIO_OUT_SET is $0xd000\_0014$ and GPIO_OUT_CLR is $0xd000\_0018$

What is the base address for IO_BANK0_BASE in the RP2040 SDK?

$$0x40014000$$

In the RP2040 GPIOx_CTRL register, what does setting FUNCSEL to 5 accomplish?

It selects the SIO function for that GPIO pin

What logic functions are available in the IO Bank GPIOx_CTRL register via IRQOVER, INOVER, OEOVER, and OUTOVER?

Inversion and Override logic (e.g., don't invert, invert, drive low, drive high)

According to the RP2040 IO Bank input procedure, what register must be adjusted to set pull up/down resistors?

The Pad Control GPIOx Register

How are GPIO pins organized in the STM32U545?

They are split into smaller groups of up to $16$ pins called Ports (e.g., A to J)

In the STM32U545, what register is used to enable the clock signal for an I/O Port?

The RCC AHB2 peripheral clock enable register 1

What is the bit value in GPIOx_MODER required to set a pin to General Purpose Output mode on the STM32U545?

$$0b01$$

What is the base address of the RCC for the STM32U545RE?

$$0x4602\_0C00$$

What is the address offset for the GPIOx_IDR (Input Data Register) in the STM32U545?

$$0x10$$

What are the four layers of the Rust Embedded Stack described in the lecture?

Framework (Tasks/Network), BSC (Board Support Crate), HAL Implementation, and PAC (Platform Access Crate)

What is the role of the Platform Access Crate (PAC) in the Rust Embedded Stack?

It accesses registers and is usually created automatically from SVD files

What are the two required methods for the InputPin trait in the Rust Embedded HAL?

fn is_high and fn is_low

Which enum is used to represent the state of an output pin in the Rust Embedded HAL?

PinState { Low, High }

What are the two primary rules for a Rust bare metal main function?

1. Never exit the main function; 2. Add a panic handler that does not exit

In a bare metal Rust application, what is provided by the #[entry] attribute?

It defines the entry point of the application (the main function)

In the bare metal RP2 application example, what is the address for GPIO_OUT_SET used to drive a pin high?

$$0xd000\_0014$$

For the STM32U545RE bare metal example, how is the GPIOx_BASE_ADDR calculated?

$$0x4202\_0000 + 0x400 \times PORT\_x$$

What framework is described as 'Embedded Asynchronous' and uses the rust-embedded-hal?

embassy-rs

Name four features of the embassy-rs framework mentioned in the transcript.

Real-time, Low power, Networking (Bluetooth/USB), and Bootloader/DFU

In embassy-rs for STM32, how is an input pin initialized?

Input::new(p.PC13, Pull::Down)

In embassy-rs for STM32, what three parameters are passed to Output::new?

The pin (e.g., p.PA5), the initial Level, and the Speed

What is the main function signature when using the embassy-rs framework?

[embassy_executor::main] async fn main(_spawner: Spawner)

In the Tock-registers example, what structure is generated to represent peripheral registers?

A C-style register_struct (e.g., SysCtrl)

What is the reset value of the CPUID register for the RP2040 according to the SVD example?

$$0x410cc601$$

In the STM32U545, what MODER bit setting corresponds to configuring a pin as an input?

$$0b00$$

What is the base address for SRAM in the Cortex-M33 memory layout?

$$0x20000000$$