CW1 Reviewer - Key Concepts in Digital Logic and Computer Architecture

Bandwidth

The maximum rate in millions of bits per second at which information can be transferred to or from a memory unit.

m-bit Register

An ordered set of m flip-flops designed to store an m-bit word.

Combinational Function

The mapping of 2n input combinations of n binary variables onto the output values 0 and 1.

Magnitude Comparator

A circuit used to compare the magnitude of two binary numbers.

Synthesis

The converse problem of determining a system structure that exhibits a given behavior.

Encoder

A circuit intended to generate the address or index of an active input line.

Analysis

The task of determining a system's structure or behavior.

Bus

A set of wires designed to transfer all bits of a word from a specified destination on the same or a different IC; the source and destination are typically registers.

Table Lookup

The process of reading stored information from a ROM.

Benchmarks

A set of actual programs that are representative of a particular computing environment that can be used for performance evaluation.

Decoder

A combinational circuit with input lines X and output lines Z such that each possible input combination applied to X activates a corresponding output line.

Structural Description

The property of a system whereby names components and defines their interconnection within the system.

Field-Programmable Gate Array

A two-dimensional array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable; the cells are linked to one another by programmable buses.

Multiplexer

A device intended to route data from one of several sources to a common destination.

Sequential Circuit

A combinational circuit and a set of flip-flops.

Hardware Description Language

A technology-independent description of digital circuits at various levels of abstraction, primarily the gate and register levels.

Components

A computer system which is defined informally as a collection of these objects.

Register-level System

A set of registers linked by combinational data-transfer and data-processing circuits.

Counter

A sequential circuit designed to cycle through a predetermined sequence of distinct states.

Gate-level Design

Concerned with processing binary variables whose possible values are restricted to bits 0 and 1.

Computer

An example of a system, defined informally as a collection of components that are connected to form a coherent entity with a specific function or purpose.

Graph

Often defined by a diagram in which nodes are represented by circles, dots, or other symbols and edges are represented by lines.

Block Diagram

A diagram where it is convenient to draw each node as a block or box in which its name/function can be written.

Behavioral Structure/Description

Enables one to determine for any given input signal to the system, its corresponding output.

Truth Table

Tabulation of all possible combinations of input/output values.

Schematic Diagram

A diagram used to identify the functions of the components of a system.

Entity

A formal statement of the system structure at the highest level as a single component.

Architecture

Specifies behavior and/or internal structure.

CAD Editors or Translators

Convert design data into forms such as HDL descriptions or schematic diagrams, which humans, computers, or both can efficiently process.

Simulators

Create computer models of a new design, which can mimic the new design's behavior and help designers determine how well the design meets various performance and cost goals.

Synthesizers

Automate the design process itself by deriving structures that implement all or part of some design step.

Heuristics

Computationally efficient but inexact methods and form the basis of most practical CAD tools.

Processor Level

Also called the architecture, behavior, or system level.

Edge Triggering

Confines the flip-flop's state changes to a narrow window of time around one edge of CK.

Demultiplexer

A circuit that routes data from a common source to one of several destinations.

Shift Register

A register designed to shift the contents of a register in and out 1 bit at a time.

Programmable Logic Devices

ICs containing many gates or other general-purpose cells whose interconnections can be programmed to implement any desired combinational or sequential function.

I-unit

Responsible for the CPU's interpretation of instructions.

Register Files

Modern CPUs retain special registers for multiplication and division, but the Accumulator and the Data Register are usually replaced by this set of general-purpose registers.

Multicycle Processing

(not Polyphase)

In this type of ALU processing, each step processes a separate m-bit slice of each operand.

Immediate Addressing

An addressing scheme where the value V(X) of the target operand is contained in the address field itself.

Throughput

This is a measure of a pipeline's performance in terms of millions of instructions executed per second.

Datapath

This part of the CPU is responsible for executing arithmetic and logical instructions on various operand types.

Orthogonality

The ability to use all addressing modes in a uniform and consistent way with all opcodes of an instruction set or assembly language.

Control Fields

Part of a microinstruction that specifies the control signals to be activated.

Floating-point (Processor)

Typically composed of a pair of fixed-point ALUs—one to process exponents and the other to process mantissas.

Absolute Addressing

Requires the complete operand address to appear in the instruction operand field.

Accumulator

Used to store an input or output operand (result) in the execution of many instructions.

Polyphase

(not Multicycle Processing)

This mode of operation permits a single microinstruction to specify a short sequence of microinstructions for some increase in the complexity of the microinstruction format.

Instruction Set

Defines the function performed by the CPU.

Pipeline Processor

Consists of a sequence of m data-processing circuits, called stages or segments, which collectively perform a single operation on a stream of data operands passing through them.

Instruction

The purpose of this is to specify both an operation to be carried out by the CPU or other processor and the set of data to be used in the operation.

Normalized

The mantissa is said to be in this state if the digit to the right of the radix point is not zero.

EDVAC

differed from most of its predecessors in that it stored and processed numbers in true binary or base 2 form. To minimize hardware costs, data was processed serially, or bit by bit.