Computer Architecture & Assembly Language Programming Vocabulary

Vocabulary terms and definitions covering x86 assembly language, memory management, interrupts, multitasking, and peripheral interfacing based on lecture notes.

ASCII Code

Stands for American Standard Code for Information Interchange; a standard numeric representation of all commonly used characters assigned from 0 to 127, later extended to 255.

B8000

The fixed physical memory location where the IBM PC text mode color display video memory is mapped.

VGA (Video Graphics Adapter)

The component in a computer that interprets numbers and performs the task of showing character shapes by glowing specific pixels on the CRT.

Attribute Byte

A byte following the ASCII code in video memory that holds the background and foreground colors (RGB) and the intensity/blinking bit for a character.

DIV Instruction

Performs unsigned division; if the operand is a byte, it divides the 16-bit value in AX; if a word, it divides the 32-bit value in DX:AX.

Divide Overflow Error

An interrupt generated when the quotient of a division exceeds the capacity of the destination register (e.g., dividing by zero).

MUL Instruction

Performs unsigned multiplication; 8-bit source multiplies by AL (result in AX), and 16-bit source multiplies by AX (result in DX:AX).

Screen Location Formula

The calculation used to find a memory offset from 2D coordinates: $\text{location} = (\text{row} \times 80 + \text{column}) \times 2$.

STOS (Store String)

Transfers a byte or word from AL or AX to the memory addressed by ES:DI and updates DI based on the Direction Flag.

LODS (Load String)

Transfers a byte or word from the source location DS:SI to AL or AX and updates SI.

SCAS (Scan String)

Compares AL or AX with the memory element addressed by ES:DI, updates flags, and increments/decrements DI.

MOVS (Move String)

Transfers a byte or word from the source location DS:SI to the destination ES:DI and updates both SI and DI.

CMPS (Compare String)

Subtracts the source location DS:SI from the destination location ES:DI to check for equality, updating SI and DI.

REP Prefix

A hardware-coded instruction prefix that repeats a following string instruction CX times, decrementing CX with each iteration.

Direction Flag (DF)

A flag in the flags register that controls the auto-increment (cleared via CLD) or auto-decrement (set via STD) mode of string instructions.

LES/LDS Instructions

Instructions that load a 32-bit segment-offset pair from memory into ES (LES) or DS (LDS) and a general-purpose register.

Interrupt Vector Table (IVT)

A table located at physical memory address zero containing 256 four-byte entries (vectors) for mapping interrupt numbers to handler addresses.

IRET

A special return instruction for interrupts that pops the Instruction Pointer (IP), the Code Segment (CS), and the Flags register from the stack.

PIC (Programmable Interrupt Controller)

The 8259 chip that manages multiple external device interrupt requests (IRQs) and forwards them to the processor's single INT pin.

IRQ (Interrupt Request)

Hardware lines (IRQ 0 to IRQ 7) used by devices like the timer, keyboard, or parallel port to signal the interrupt controller.

PIT (Programmable Interval Timer)

The 8254 chip with a precise input frequency of $1.19318\,MHz$, used to generate the system timer tick 18.2 times per second.

TSR (Terminate and Stay Resident)

A program that remains in memory after execution by using DOS service 31h, allowing it to provide background services or hook interrupts.

Paragraph

A unit of memory measurement in x86 architecture equal to $16\,\text{bytes}$; used in TSR memory allocation.

Scan Code

A unique number sent by the keyboard controller for every key press (bit 7 clear) and release (bit 7 set) to identify the key.

PCB (Process Control Block)

A storage area where the scheduler saves all registers and state information for a task in a multitasking system.

Context Switch

The process of saving the registers of a currently running task and restoring the registers of the next task to be executed.

Protected Mode

A 32-bit processor mode enabled by setting the least significant bit of the CR0 register, featuring a 4GB address space and privilege levels.

GDT (Global Descriptor Table)

An array of 8-byte descriptors that define the base address, limit, and attributes for memory segments in protected mode.

Calling Conventions

Standard behaviors for high-level languages (like C or Pascal) defining parameter passing order, stack cleanup, and register preservation.

Register Window

A concept in SPARC processors where sets of 'in', 'local', and 'out' registers change during function calls to avoid saving/restoring registers to the stack.