Design Rationale & Trade-offs

Why did you use AXI4-Lite instead of full AXI4?

The UART only needs single 32-bit register reads and writes. Full AXI4 adds bursts, IDs, and out-of-order support I would never use, which means more handshake logic and more verification for zero benefit. AXI4-Lite is the standard subset for memory-mapped peripheral registers, and the Zynq GP master port speaks it directly.

Why are the FIFOs 16 deep?

16 absorbs a CPU burst while the serial line drains slowly, the occupancy fits in the 5-bit status fields, and a power of two is required by my pointer scheme. Deeper would cost more flip flops for no real gain at UART speeds. The RTL enforces power-of-two depth with an elaboration-time check.

Why must Fifo_Slots be a power of two?

The full/empty detection uses pointers with one extra MSB and relies on natural binary wraparound of the lower bits. Non-power-of-two depths break that wrap math, so I check (Fifo_Slots & (Fifo_Slots - 1)) != 0 in an initial block and kill the sim at elaboration if it fails.

Why asynchronous active-low reset instead of synchronous?

Every clocked block is always @(posedge Clk or negedge Rst_N), so reset takes effect even without a running clock, and active-low matches common board and Zynq conventions. The cost is visible in synthesis: the design maps to FDCE (async clear) cells instead of FDRE for the control logic.

Why did you convert the RX FIFO output Data_Out from a registered output to a combinational wire?

The AXI read wants to capture the head byte and pop the FIFO on the same clock edge. With a registered output the byte appears one cycle after the pop, so every AXI read returned the previous byte. I found this in simulation: sending A1 B2 C3 read back as 00 A1 B2. Making Data_Out a continuous assign of the head slot (first-word fall-through) fixed it with no change to the AXI wrapper.

What is the trade-off of first-word fall-through versus a registered FIFO output?

FWFT gives a zero-latency read, which the same-cycle AXI read needs. The cost is the FIFO read mux sits combinationally on the output path instead of a clean flop-to-flop path. At 16 deep and 100 MHz that is trivial, but on a deep, fast FIFO the registered version times better, which is why both styles exist in Xilinx FIFO IP.

Why 16x oversampling in the receiver instead of sampling once per bit?

The start edge arrives asynchronously, so I need sub-bit resolution to find it, wait half a bit, and then sample every bit at its center. Oversampling also gives tolerance to baud mismatch between the two ends and enables the mid-bit start recheck that rejects glitches.

Why is the TX baud counter held at zero while the transmitter is idle?

So the first bit period is exactly one baud period starting at the frame start. A free-running divider would make the first bit anywhere from zero to one full period long depending on where the counter happened to be when the frame started.

Why did you add Write_Address_Q and Write_Data_Q latches in the AXI wrapper?

AXI allows the master to deassert and reuse the address bus after the AW handshake, before W arrives. My commit logic runs later, when both handshakes are done, so it must use latched copies. I proved the bug first: a spec-legal master that moved the address bus caused a byte intended for TX_DATA to be written into the Control register.

Why is the status register combinational instead of registered?

It is a wire built from continuous assigns of the live flags and occupancies, so an AXI read always returns the current hardware state. A registered copy could be a cycle stale, and there is no timing pressure that would justify registering it.

Why did you avoid vendor IP entirely?

Portability and understanding. The TX and RX blocks are plain Verilog so they work standalone on any FPGA, and I can defend every line rather than pointing at a black box. The only Zynq-specific part of the project is where the clock and AXI master come from.

Why is Address_Width 4 bits?

Four registers at word-aligned offsets 0x0, 0x4, 0x8, 0xC. Four bits covers the map, keeps the case decode a single nibble compare, and leaves room for future registers like a baud divisor.

Why do the FIFO pointers carry one extra MSB?

With equal-width pointers, full and empty both look like pointer equality. The extra bit disambiguates: empty is full equality including the MSB, full is lower bits equal with MSBs different. It also lets Occupancy = Write_Pointer - Read_Pointer represent the value 16.

Why 8N1 framing only?

It is the dominant UART configuration and keeps both FSMs at four states. Parity and configurable frame format are on the roadmap; STATUS bit 3 is already reserved for parity error.