7. RISC-V Pipeline

What are the 5 stages of the RISC-V integer pipeline and where do buffers exist?

The RISC-V integer pipeline contains 5 stages:

• IF

• ID

• EXE

• MEM

• WB

Pipeline Buffers:

• Buffers exist between stages: IF/ID, ID/EX, EX/MEM, and MEM/WB.

• These buffers store intermediate values between clock cycles.

What is a Multiplexer (MUX) and how many are used in the RISC-V pipeline?

The pipeline uses 4 multiplexers for control.

A multiplexer (MUX) is a hardware component that selects one of multiple inputs and forwards it to the output.

In pipelines, they choose between:

• Different operand sources

• Different addresses

• Normal or forwarded values

What are the specific functions of the IF MUX and the EXE Stage MUXes?

IF MUX:

• Chooses between PC + 4 or the Branch target address.

• Used to determine the next instruction address.

EXE Stage MUXes:

• Top MUX: Used for branch instructions.

• Bottom MUX: Chooses between R-format operands or I-format immediate values.

What is the function of the Writeback MUX?

Writeback MUX:

• Chooses whether the written value comes from the MEM/WB buffer or a forwarded value.

What are control signals and how are they managed in the pipeline?

Control Signals:

• Generated during the ID stage.

• A control signal is a binary signal that tells hardware components what operation to perform.

• Signals are passed through the pipeline to later stages to control MUXes, ALU operations, memory access, register writes, and pipeline operations.

What are Functional Units and in which stage do they primarily operate?

Functional Units:

• A pipeline may contain multiple functional units.

• They operate mainly during the EXE stage.

• Examples: Integer ALU, FP Add, FP Multiply, Integer Multiply, FP Divide, Integer Divide, and Memory unit.

How are Latency and Initiation Interval defined for functional units?

Latency:

• Number of cycles until the result is produced (measured relative to the next instruction).

Initiation Interval:

• Number of cycles required between starting consecutive operations using the same functional unit.

• Measured from the start of one operation to the start of the next.

Based on the functional unit table, what are the Latency and Initiation Intervals for typical operations?

Functional Unit	Latency	Initiation Interval
Integer ALU	0	1
Memory (Int/FP loads)	1	1
FP Add	3	1
FP/Integer Multiply	6	1
FP/Integer Divide	24	25

Note: Multiplication and division have high latency; division is significantly higher.

What is the difference between pipelined and non-pipelined functional units?

Internally Pipelined:

• The operation is divided into stages.

• Multiple operations can overlap in execution.

• Examples: Multipliers and dividers are often internally pipelined.

Non-pipelined:

• A new operation cannot start until the current one finishes.

How are Register Files organized in RISC-V and why?

Organization:

• Integer and floating-point operations use separate register files.

• Integer instructions use integer registers

What are the exceptions to the rule of separate Register Files?

Exceptions:

• FP load/store instructions: Use integer registers as addresses.

• Register move instructions: Can transfer data between FP and integer registe