Structure and Function of a Processor

Arithmetic and Logic Unit

Arithmetic and Logic Unit

performs logical operations and arithmetic calculations (inc binary shift and <>=+-*/)

Control Unit

• controls flow of data in CPU

• in the decode stage, opcode (operation code) and operand (value or expression needed to perform operation) are analysed to find out what to execute

• directs operations of other components

• uses control signals to enable reading/writing to memory and determine operation ALU carries out

Program Counter

holds address of the next instruction to be fetched by the processor

Accumulator

Temporarily stores inputted/loaded values or results of calculations and logical operations by the ALU 

Memory Data Register (MDR) 

Temporarily holds data values or instructions that are read from or written to main memory (before sent to memory or after being fetched) 

Memory Address Register

Temporarily holds address of memory location (in main memory) that the processor needs to access/read from/write to (where being sent or where being fetched from) 

Current Instruction Register

After an instruction is fetched it is sent here - Holds the current instruction that the processor is executing, divided into operand and opcode 

Status Flags

In the ALU, status flags send signals to the processor to interrupt it and alert it to a problem such as an overflow or a zero

Data Bus

• transfers data and instructions to/from CPU and RAM

• bidirectional

• read/write

Address Bus

• transfers memory addresses specifying where data is to be sent

• unidirectional; only goes from CPU to memory

  • read/write (I think)

Control Bus

• Transmits control signals between internal and external components 

  • Bidirectional (goes from CPU from/to input/output and CPU from/to memory)

• Coordinates the use of the address and data buses and provides status information between components 

• Sends signals to determine whether other buses are in read/write mode 

Von Neumann Architecture

• Shared memory space for instructions and data in the same format 

• Single CU follows a linear FDE cycle 

• One instruction at a time 

• Registers offer fast data access 

• From the 1940s 

Harvard Architecture

• Instructions and data stored in separate memory units with separate buses 

• Reading and writing is done at the same time as fetching instructions 

  • From the 1940s 

Contemporary architectures (a big chonky one)

• SIMD= parallel processing, processor carries out single instruction on multiple data

• MIMD= multiple instructions carried out on multiple data across several cores

• Distributed computing= multiple computers on a shared network each take on part of a bigger problem